Wait State Control - Hitachi SH7095 Hardware User Manual

7.4.2

Wait State Control

The number of wait states inserted into ordinary space access states can be controlled using the
WCR and BCR1 register settings. When the Wn1 and Wn0 wait specification bits of the WCR for
the given CS space are 01 or 10, soft waits are inserted according to the wait specification. When
Wn1 and Wn0 are 11, wait cycles are inserted according to the long wait specification bit AnLW
of BCR1. The long wait specification of BCR1 can be made independently for CS0 and CS1
spaces, but the same value must be specified for CS2 and CS3 spaces. All WCR specifications are
independent. A Tw cycle as long as the number of specified cycles is inserted as a wait cycle at the
wait timing for ordinary access space shown in figure 7.11.
Figure 7.11 Wait Timing of Ordinary Space Access (Software Wait Only)
When the wait is specified by software using WCR, the wait input WAIT signal from outside is
sampled. Figure 7.12 shows the WAIT signal sampling. A 2-cycle wait is specified as a software
wait. The sampling is performed when the Tw state shifts to T2 state, so there is no effect even
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