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Bits 1 and 0—Wait Count 1 and 0 (WC1/0): These bits select the number of wait states inserted
in access to external three-state-access areas.
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Bit 1
Bit 0
WC1
WC0
0
0
1
1
0
1
6.2.4 Wait State Controller Enable Register (WCER)
WCER is an 8-bit readable/writable register that enables or disables wait-state control of external
three-state-access areas by the wait-state controller.
Bit
WCE7
Initial value
Read/Write
R/W
WCER is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0—Wait-State Controller Enable 7 to 0 (WCE7 to WCE0): These bits enable or
disable wait-state control of external three-state-access areas.
Bits 7 to 0
WCE7 to WCE0
Description
0
Wait-state control disabled (pin wait mode 0)
1
Wait-state control enabled
Since WCER enables or disables wait-state control of external three-state-access areas, these
settings are meaningless in single-chip mode (mode 7).
Description
No wait states inserted by wait-state controller
1 state inserted
2 states inserted
3 states inserted
7
6
5
WCE6
WCE5
1
1
1
R/W
R/W
Wait-state controller enable 7 to 0
These bits enable or disable wait-state control
4
3
2
WCE4
WCE3
WCE2
1
1
1
R/W
R/W
R/W
117
(Initial value)
1
0
WCE1
WCE0
1
1
R/W
R/W
(Initial value)
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