Figure 22.25 Basic Bus Cycle: Three-State Access With One Wait State; Figure 22.26 Bus-Release Mode Timing - Hitachi H8/3062 Hardware Manual

φ
A to A ,
23 0
CS
n
AS
RD (read)
D to D
15 0
(read)
HWR, LWR
(write)
D to D
15 0
(write)
WAIT

Figure 22.25 Basic Bus Cycle: Three-State Access with One Wait State

φ
t
BREQ
BACK
A to A ,
23 0
AS, RD,
HWR, LWR
T T
1 2
t t
WTS WTH
BRQS

Figure 22.26 Bus-Release Mode Timing

T
W
t
t
WTS
WTH
t
BRQS
t
BACD1
t
BZD
T
3
t
BACD2
t
BZD
759