Bus Width Control Register (Abwcr); Access State Control Register (Astcr) - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

• Refresh time constant register (RTCOR)
6.3.1

Bus Width Control Register (ABWCR)

ABWCR designates each area in the external address space as either 8-bit access space or 16-bit
access space.
Bit Bit Name
7 ABW7
6 ABW6
5 ABW5
4 ABW4
3 ABW3
2 ABW2
1 ABW1
0 ABW0
Note: In modes 2, 4, and 6, ABWCR is initialized to 1. In modes 1, 5, and 7, ABWCR is initialized
to 0.
6.3.2

Access State Control Register (ASTCR)

ASTCR designates each area in the external address space as either 2-state access space or 3-state
access space.
Bit Bit Name
7 AST7
6 AST6
5 AST5
4 AST4
3 AST3
2 AST2
1 AST1
0 AST0
Rev. 1.0, 09/01, page 110 of 904
Initial Value* R/W
1/0 R/W
1/0 R/W
1/0 R/W
1/0 R/W
1/0 R/W
1/0 R/W
1/0 R/W
1/0 R/W
Initial Value R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Description
Area 7 to 0 Bus Width Control
These bits select whether the corresponding
area is to be designated as 8-bit access space
or 16-bit access space.
0: Area n is designated as 16-bit access space
1: Area n is designated as 8-bit access space
Description
Area 7 to 0 Access State Control
These bits select whether the corresponding
area is to be designated as 2-state access
space or 3-state access space. Wait state
insertion is enabled or disabled at the same
time.
0: Area n is designated as 2-state access space
Wait state insertion in area n access is disabled
1: Area n is designated as 3-state access space
Wait state insertion in area n access is enabled
(n = 7 to 0)
(n = 7 to 0)