Wait State Control Register 1 (Wcr1) - Hitachi SH7709S Hardware Manual

Bit 2n + 1: AnSZ1 Bit 2n: AnSZ0
0 0
1
1 0
1
0 0
1
1 0
1
10.2.3

Wait State Control Register 1 (WCR1)

Wait state control register 1 (WCR1) is a 16-bit readable/writable register that specifies the
number of idle (wait) state cycles inserted for each area. For some memories, data bus drive may
not be turned off quickly even when the read signal from the external device is turned off. This
can result in conflicts between data buses when consecutive memory accesses are to different
memories or when a write immediately follows a memory read. This LSI automatically inserts the
number of idle states set in WCR1 in those cases.
WCR1 is initialized to H'3FF3 by a power-on reset. It is not initialized by a manual reset or in
standby mode, and retains its contents.
Bit:
WAITSEL
Initial value:
R/W: R/W
Bit:
A3IW1
Initial value:
R/W: R/W
244
Port A / B
Not used
Used
15 14 13
— A6IW1
0 0 1
R R/W
7 6 5
A3IW0 A2IW1
1 1 1
R/W R/W
Description
Reserved (Setting prohibited)
Byte (8-bit) size
Word (16-bit) size
Longword (32-bit) size
Reserved (Setting prohibited)
Byte (8-bit) size
Word (16-bit) size
Reserved (Setting prohibited)
12 11 10
A6IW0 A5IW1 A5IW0
1 1 1
R/W R/W R/W
4 3 2
A2IW0 — —
1 0 0
R/W R R
9 8
A4IW1 A4IW0
1 1
R/W R/W
1 0
A0IW1 A0IW0
1 1
R/W R/W