Figure 24.9 Basic Bus Timing (Three-State Access With One Wait State) - Hitachi H8S/2215 Series Hardware Manual

Hitachi single-chip microcomputer
Table of Contents

Advertisement

ø
A23 to A0
to
(read)
D15 to D0
(read)
,
(write)
D15 to D0
(write)

Figure 24.9 Basic Bus Timing (Three-State Access with One Wait State)

T1
T2
t
t
WTS
WTH
TW
t
t
WTS
WTH
Rev. 3.0, 10/02, page 661 of 686
T3

Advertisement

Table of Contents
loading

Table of Contents