Table of Contents
Advertisement
Bits 7 to 0—Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select 8-bit access or
16-bit access for the corresponding areas.
Bits 7 to 0
ABW7 to ABW0
0
1
ABWCR specifies the data bus width of external memory areas. The data bus width of on-chip
memory and registers is fixed, and does not depend on ABWCR settings. These settings are
therefore invalid in the single-chip modes (modes 6 and 7).
6.2.2
Access State Control Register (ASTCR)
ASTCR is an 8-bit readable/writable register that selects whether each area is accessed in two
states or three states.
7
Bit
AST7
Initial value
1
Read/Write
R/W
ASTCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0—Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the
corresponding area is accessed in two or three states.
Bits 7 to 0
AST7 to AST0
0
1
ASTCR specifies the number of states in which external areas are accessed. On-chip memory and
registers are accessed in a fixed number of states that does not depend on ASTCR settings. These
settings are therefore meaningless in the single-chip modes (modes 6 and 7).
Description
Areas 7 to 0 are 16-bit access areas
Areas 7 to 0 are 8-bit access areas
6
5
AST6
AST5
1
1
R/W
R/W
Bits selecting number of states for access to each area
Description
Areas 7 to 0 are accessed in two states
Areas 7 to 0 are accessed in three states
4
3
AST4
AST3
1
1
R/W
R/W
2
1
AST2
AST1
1
1
R/W
R/W
(Initial value)
0
AST0
1
R/W
125
Advertisement
Table of Contents
