Hitachi H8/300H Series Programming Manual
  1. Manuals
  2. Brands
  3. Hitachi Manuals
  4. Computer Hardware
  5. H8/300H Series
  6. Programming manual
Hitachi H8/300H Series Programming Manual

Hitachi H8/300H Series Programming Manual

Hide thumbs
Table of Contents

Advertisement

Quick Links

H8/300H Series
Programming Manual
HITACHI
ADE-602-053A

Advertisement

Table of Contents
loading

Related Manuals for Hitachi H8/300H Series

Summary of Contents for Hitachi H8/300H Series

  • Page 1 H8/300H Series Programming Manual HITACHI ADE-602-053A...
  • Page 2 Major Revisions and Additions in this Version Page Item Description Figure 1-12 Instruction Formats Figure (4) amended Table 1-6 Effective Address Calculation (8) Table amended 2.2.6 BAND Notes added 2.2.11 BIOR Operand Format and Number of Register direct 1st byte States Required for Execution amended 2.2.18 BSR...
  • Page 3 Page Item Description P175 2.2.58 (2) STC (W) Instruction amended 2.2.58 (2) STC (W) Assembler Format Assembler format amended P176 2.2.58 (2) STC (W) Operand Format and Number of Mnemonic amended States Required for Execution P180 2.2.60 SUBS Operation Operation amended P189 (1) Data Transfer Instructions MOV.W @ERs+,Rd Operation amended...

  • Page 4: Table Of Contents

    Contents Section 1 ........................Overview......................... 1.1.1 Features....................... 1.1.2 Differences from H8/300 CPU ................CPU Operating Modes....................Address Space......................... Register Configuration....................1.4.1 Overview......................1.4.2 General Registers....................1.4.3 Control Registers ....................10 1.4.4 Initial Register Values..................11 Data Formats........................12 1.5.1 General Register Data Formats................12 1.5.2 Memory Data Formats..................
  • Page 5 2.2.6 BAND......................51 2.2.7 Bcc......................... 52 2.2.8 BCLR......................54 2.2.9 BIAND ......................56 2.2.10 BILD......................57 2.2.11 BIOR......................58 2.2.12 BIST ......................59 2.2.13 BIXOR......................60 2.2.14 BLD ....................... 61 2.2.15 BNOT ......................62 2.2.16 BOR....................... 64 2.2.17 BSET ......................65 2.2.18 BSR........................
  • Page 6 2.2.34 (2) LDC (W)......................109 2.2.35 (1) MOV (B) ....................... 111 2.2.35 (2) MOV (W) ...................... 112 2.2.35 (3) MOV (L)......................113 2.2.35 (4) MOV (B) ....................... 114 2.2.35 (5) MOV (W) ...................... 116 2.2.35 (6) MOV (L)......................118 2.2.35 (7) MOV (B) ....................... 120 2.2.35 (8) MOV (W) ......................
  • Page 7 2.2.50 (2) ROTXR (W) ....................157 2.2.50 (3) ROTXR (L) ....................158 2.2.51 RTE........................ 159 2.2.52 RTS ........................ 160 2.2.53 (1) SHAL (B) ...................... 161 2.2.53 (2) SHAL (W) ..................... 162 2.2.53 (3) SHAL (L)....................... 163 2.2.54 (1) SHAR (B) ...................... 164 2.2.54 (2) SHAR (W) .....................
  • Page 8 3.3.2 Exception-Handling Sequences ................242 Bus-Released State ......................244 Reset State ........................244 Power-Down State ......................244 3.6.1 Sleep Mode ......................244 3.6.2 Software Standby Mode ..................244 3.6.3 Hardware Standby Mode ..................244 Section 4 Basic Timing ....................245 Overview.........................

  • Page 9: Section 1 Cpu

    Section 1 CPU 1.1 Overview The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. 1.1.1 Features The H8/300H CPU has the following features.

  • Page 10: Differences From H8/300 Cpu

    — 8/16/32-bit register-register add/subtract: 125 ns — 8 × 8-bit register-register multiply: 875 ns — 16 ÷ 8-bit register-register divide: 875 ns — 16 × 16-bit register-register multiply: 1375 ns — 32 ÷ 16-bit register-register divide: 1375 ns • Two CPU operating modes —...

  • Page 11: Cpu Operating Modes

    1.2 CPU Operating Modes The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports up to 16 Mbytes. The mode is selected at the mode pins of the microcontroller. For further information, refer to the relevant hardware manual.
  • Page 12 H'0000 Reset exception vector H'0001 H'0002 H'0003 Reserved for system use H'0004 H'0005 Exception vector table H'0006 Exception vector 1 H'0007 H'0008 Exception vector 2 H'0009 Figure 1-2 Exception Vector Table (normal mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address to specify a memory operand that contains a branch address.
  • Page 13 (2) Advanced Mode: In advanced mode the exception vector table and stack structure differ from the H8/300 CPU. Address Space: Up to 16 Mbytes can be accessed linearly. Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit data registers, or they can be combined with the general registers (R0 to R7) for use as 32-bit data registers.
  • Page 14 The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, of which the lower 24 bits are the branch address. Branch addresses can be stored in the top area from H'000000 to H'0000FF.

  • Page 15: Address Space

    1.3 Address Space Figure 1-6 shows a memory map of the H8/300H CPU. (a) Normal mode (b) Advanced mode H'0000 H'000000 H'FFFF H'FFFFFF Figure 1-6 Memory Map...

  • Page 16: Register Configuration

    1.4 Register Configuration 1.4.1 Overview The H8/300H CPU has the internal registers shown in figure 1-7. There are two types of registers: general and extended registers, and control registers. General registers (Rn) and extended registers (En) Control registers (CR) 7 6 5 4 3 2 1 0 I U H U N Z V C Legend Stack pointer...

  • Page 17: General Registers

    1.4.2 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used without distinction between data registers and address registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or as address registers, they are designated by the letters ER (ER0 to ER7).

  • Page 18: Control Registers

    General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 1-9 shows the stack. Free area SP (ER7) Stack area Figure 1-9 Stack 1.4.3 Control Registers The control registers are the 24-bit program counter (PC) and the 8-bit condition-code register (CCR).

  • Page 19: Initial Register Values

    Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise.

  • Page 20: Data Formats

    1.5 Data Formats The H8/300H CPU can process 1-bit, 4-bit, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.

  • Page 21: Memory Data Formats

    Word data Word data Longword data Legend ERn: General register ER General register E General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 1-10 General Register Data Formats (cont) 1.5.2 Memory Data Formats Figure 1-11 shows the data formats on memory.
  • Page 22 Data type Data format Address 1-bit data Address L Byte data Address L Word data Address 2M Address 2M + 1 Longword data Address 2N Address 2N + 1 Address 2N + 2 Address 2N + 3 Figure 1-11 Memory Data Formats When ER7 is used as an address register to access the stack, the operand size should be word size or longword size.

  • Page 23: Instruction Set

    1.6 Instruction Set 1.6.1 Overview The H8/300H CPU has 62 types of instructions, which are classified by function in table 1-1. For a detailed description of each instruction see section 2.2, Instruction Descriptions. Table 1-1 Instruction Classification Function Instructions Number Data transfer MOV, PUSH , POP...

  • Page 24: Instructions And Addressing Modes

    1.6.2 Instructions and Addressing Modes Table 1-2 indicates the instructions available in the H8/300H CPU. Table 1-2 Instruction Set Overview Addressing Modes Function Instruction @ERn @(d:16,ERn) @(d:24,ERn) @ERn+/@–ERn @aa:8 @aa:16 @aa:24 @(d:8,PC) @(d:16,PC) @@aa:8 — Data — — — — transfer POP, PUSH —...
  • Page 25 Table 1-2 Instruction Set Overview (cont) Addressing Modes Function Instruction @ERn @(d:16,ERn) @(d:24,ERn) @ERn+/@–ERn @aa:8 @aa:16 @aa:24 @(d:8,PC) @(d:16,PC) @@aa:8 — Branch Bcc, BSR — — — — — — — — — — — — — — — — JMP, JSR —...

  • Page 26: Tables Of Instructions Classified By Function

    1.6.3 Tables of Instructions Classified by Function Table 1-3 summarizes the instructions in each functional category. The notation used in table 1-3 is defined next. Operation Notation General register (destination)* General register (source)* General register* General register (32-bit register) (EAd) Destination operand (EAs) Source operand...
  • Page 27 Table 1-3 Instructions Classified by Function Type Instruction Size* Function (EAs) → Rd, Rs → (EAd) Data transfer B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. (EAs) →...
  • Page 28 Table 1-3 Instructions Classified by Function (cont) Type Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd Arithmetic B/W/L operations Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register.
  • Page 29 Table 1-3 Instructions Classified by Function (cont) Type Instruction Size* Function Rd ÷ Rs → Rd Arithmetic DIVXU operations Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8- bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder.
  • Page 30 Table 1-3 Instructions Classified by Function (cont) Type Instruction Size* Function Rd (shift) → Rd SHAL Shift operations B/W/L SHAR Performs an arithmetic shift on general register contents. Rd (shift) → Rd SHLL B/W/L SHLR Performs a logical shift on general register contents. Rd (rotate) →...
  • Page 31 Table 1-3 Instructions Classified by Function (cont) Type Instruction Size* Function C ∨ (<bit-No.> of <EAd>) → C Bit-manipulation instructions ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag.
  • Page 32 Table 1-3 Instructions Classified by Function (cont) Type Instruction Size* Function Branching — Branches to a specified address if a specified condition instructions is true. The branching conditions are listed below. Mnemonic Description Condition BRA(BT) Always (true) Always BRN(BF) Never (false) Never C ∨...
  • Page 33 Table 1-3 Instructions Classified by Function (cont) Type Instruction Size* Function System control TRAPA — Starts trap-instruction exception handling. instructions — Returns from an exception-handling routine. SLEEP — Causes a transition to the power-down state. (EAs) → CCR Moves the source operand contents to the condition code register.
  • Page 34 Table 1-3 Instructions Classified by Function (cont) Type Instruction Size* Function if R4L ≠ 0 then Block data EEPMOV.B — transfer Repeat @ER5 +→ @ER6 + instruction R4L – 1→R4L Until R4L = 0 else next; if R4 ≠ 0 then EEPMOV.W —...

  • Page 35: Basic Instruction Formats

    1.6.4 Basic Instruction Formats The H8/300H instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (OP field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Operation Field: Indicates the function of the instruction, the effective address, and the operation to be carried out on the operand.

  • Page 36: Addressing Modes And Effective Address Calculation

    1.6.5 Addressing Modes and Effective Address Calculation (1) Addressing Modes: The H8/300H CPU supports the eight addressing modes listed in table 1- 4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect.
  • Page 37 4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn: • Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn), the lower 24 bits of which contain the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents (32 bits) and the sum is stored in the address register.
  • Page 38 7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit program counter (PC) contents to generate a branch address. The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to +16384 words) from the branch instruction.
  • Page 39 Table 1-6 Effective Address Calculation Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Register direct Operands are contents of regm and regn Regm Regn Register indirect @ERn Register contents Register indirect with displacement @(d:16, ERn) Register contents disp disp Sign extension...
  • Page 40 Table 1-6 Effective Address Calculation (cont) Effective Address (EA) Addressing Mode and Instruction Format Effective Address Calculation Absolute address @aa:8 H'FFFF @aa:16 16 15 Sign extension @aa:24 Immediate #xx:8/#xx:16/#xx:32 Operand is immediate data.
  • Page 41 Table 1-6 Effective Address Calculation (cont) Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Program-counter relative PC contents @(d:8, PC)/@(d:16, PC) disp Sign disp extension Memory indirect @@aa:8 Normal mode H'0000 16 15 Memory contents H'00 Advanced mode H'0000 Memory contents...
  • Page 42 Legend reg, regm, regn: General registers Operation field disp: Displacement abs: Absolute address IMM: Immediate data...

  • Page 43: Section 2 Instruction Descriptions

    Section 2 Instruction Descriptions 2.1 Tables and Symbols This section explains how to read the tables describing each instruction. Note that the descriptions of some instructions extend over two pages or more. Mnemonic (full name): Gives the full and mnemonic names of the instruction. Type: Indicates the type of instruction.

  • Page 44: Assembler Format

    2.1.1 Assembler Format Example: ADD. B <EAs>, Rd Destination operand Source operand Size Mnemonic The operand size is byte (B), word (W), or longword (L). Some instructions are restricted to a limited set of operand sizes. The symbol <EA> indicates that two or more addressing modes can be used. The H8/300H CPU supports the eight addressing modes listed next.

  • Page 45: Operation

    2.1.2 Operation The symbols used in the operation descriptions are defined as follows. Symbol Meaning General destination register* General source register* General register* General destination register (address register or 32-bit register) General source register (address register or 32-bit register) General register (32-bit register) (EAd) Destination operand (EAs)

  • Page 46: Condition Code

    2.1.3 Condition Code The symbols used in the condition-code description are defined as follows. Symbol Meaning Changes according to the result of the instruction Undetermined (no guaranteed value) Always cleared to 0 – Not affected by execution of the instruction ∆...

  • Page 47: Register Specification

    2.1.5 Register Specification Address Register Specification: When a general register is used as an address register [@ERn, @(d:16, ERn), @(d:24, ERn), @ERn+, or @–ERn], the register is specified by a 3-bit register field (ers or erd). The lower 24 bits of the register are valid. Data Register Specification: A general register can be used as a 32-bit, 16-bit, or 8-bit data register, which is specified by a 3-bit register number.

  • Page 48: Bit Data Access In Bit Manipulation Instructions

    2.1.6 Bit Data Access in Bit Manipulation Instructions Bit data is accessed as the n-th bit (n = 0, 1, 2, 3, …, 7) of a byte operand in a general register or memory. The bit number is given by 3-bit immediate data, or by the lower 3 bits of a general register value.

  • Page 49: Instruction Descriptions

    2.2 Instruction Descriptions The instructions are described starting in section 2.2.1.

  • Page 50: 1) Add (B)

    2.2.1 (1) ADD (B) ADD (ADD binary) Add Binary Operation Condition Code Rd + (EAs) → Rd UI H — — — Assembly-Language Format ADD.B <EAs>, Rd H: Set to 1 if there is a carry at bit 3; otherwise cleared to 0. Operand Size N: Set to 1 if the result is negative;...

  • Page 51: 2) Add (W)

    2.2.1 (2) ADD (W) ADD (ADD binary) Add Binary Operation Condition Code Rd + (EAs) → Rd UI H — — — Assembly-Language Format ADD.W <EAs>, Rd H: Set to 1 if there is a carry at bit 11; otherwise cleared to 0. Operand Size N: Set to 1 if the result is negative;...

  • Page 52: 3) Add (L)

    2.2.1 (3) ADD (L) ADD (ADD binary) Add Binary Operation Condition Code ERd + (EAs) → ERd UI H — — — Assembly-Language Format ADD.L <EAs>, ERd H: Set to 1 if there is a carry at bit 27; otherwise cleared to 0. Operand Size N: Set to 1 if the result is negative;...

  • Page 53: Adds

    2.2.2 ADDS ADDS (ADD with Sign extension) Add Binary Address Data Operation Condition Code Rd + 1 → ERd UI H Rd + 2 → ERd — — — — — — — — Rd + 4 → ERd H: Previous value remains unchanged. Assembly-Language Format N: Previous value remains unchanged.

  • Page 54: Addx

    2.2.3 ADDX ADDX (ADD with eXtend carry) Add with Carry Operation Condition Code Rd + (EAs) + C → Rd UI H — — — Assembly-Language Format ADDX <EAs>, Rd H: Set to 1 if there is a carry at bit 3; otherwise cleared to 0.

  • Page 55: 1) And (B)

    2.2.4 (1) AND (B) AND (AND logical) Logical AND Operation Condition Code Rd ∧ (EAs) → Rd UI H — — — — — Assembly-Language Format AND.B <EAs>, Rd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise Operand Size cleared to 0.

  • Page 56: 2) And (W)

    2.2.4 (2) AND (W) AND (AND logical) Logical AND Operation Condition Code Rd ∧ (EAs) → Rd UI H — — — — — Assembly-Language Format AND.W <EAs>, Rd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise Operand Size cleared to 0.

  • Page 57: 3) And (L)

    2.2.4 (3) AND (L) AND (AND logical) Logical AND Operation Condition Code ERd ∧ (EAs) → ERd UI H — — — — — Assembly-Language Format AND.L <EAs>, ERd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise Operand Size cleared to 0.

  • Page 58: Andc

    2.2.5 ANDC ANDC (AND Control register) Logical AND with CCR Operation Condition Code CCR ∧ #IMM → CCR UI H Assembly-Language Format ANDC #xx:8, CCR Stores the corresponding bit of the result. UI: Stores the corresponding bit of the result Operand Size H: Stores the corresponding bit of the result.

  • Page 59: Band

    2.2.6 BAND BAND (Bit AND) Bit Logical AND Operation Condition Code C ∧ (<bit No.> of <EAd>) → C UI H — — — — — — — Assembly-Language Format BAND #xx:3, <EAd> H: Previous value remains unchanged. N: Previous value remains unchanged. Operand Size Z: Previous value remains unchanged.

  • Page 60: Bcc

    2.2.7 Bcc Bcc (Branch conditionally) Conditional Branch Operation Condition Code If condition is true, then UI H PC + disp → PC — — — — — — — — else next; H: Previous value remains unchanged. Assembly-Language Format N: Previous value remains unchanged. Bcc disp Z: Previous value remains unchanged.
  • Page 61 Bcc (Branch conditionally) Conditional Branch Operand Format and Number of States Required for Execution Instruction Format Addressing No. of Mnemonic Operands Mode States 1st byte 2nd byte 3rd byte 4th byte disp Program-counter BRA (BT) relative d:16 disp disp Program-counter BRN (BF) relative d:16...

  • Page 62: Bclr

    2.2.8 BCLR BCLR (Bit CLeaR) Bit Clear Operation Condition Code 0 → (<bit No.> of <EAd>) UI H — — — — — — — — Assembly-Language Format BCLR #xx:3, <EAd> H: Previous value remains unchanged. BCLR Rn, <EAd> N: Previous value remains unchanged. Z: Previous value remains unchanged.
  • Page 63 BCLR (Bit CLeaR) Bit Clear Operand Format and Number of States Required for Execution Instruction Format Addressing No. of Mnemonic Operands Mode* States 1st byte 2nd byte 3rd byte 4th byte Register direct BCLR #xx:3, Rd 0 IMM Register indirect BCLR #xx:3, @ERd 0 erd...

  • Page 64: Biand

    2.2.9 BIAND BIAND (Bit Invert AND) Bit Logical AND Operation Condition Code C ∧ [¬ (<bit No.> of <EAd>)] → C UI H — — — — — — — Assembly-Language Format BIAND #xx:3, <EAd> H: Previous value remains unchanged. N: Previous value remains unchanged.

  • Page 65: Bild

    2.2.10 BILD BILD (Bit Invert LoaD) Bit Load Operation Condition Code ¬ (<bit No.> of <EAd>) → C UI H — — — — — — — Assembly-Language Format BILD #xx:3, <EAd> H: Previous value remains unchanged. N: Previous value remains unchanged. Operand Size Z: Previous value remains unchanged.

  • Page 66: Bior

    2.2.11 BIOR BIOR (Bit Invert inclusive OR) Bit Logical OR Operation Condition Code C ∨ [¬ (<bit No.> of <EAd>)] → C UI H — — — — — — — Assembly-Language Format BIOR #xx:3, <EAd> H: Previous value remains unchanged. N: Previous value remains unchanged.

  • Page 67: Bist

    2.2.12 BIST BIST (Bit Invert STore) Bit Store Operation Condition Code ¬ C → (<bit No.> of <EAd>) UI H — — — — — — — — Assembly-Language Format BIST #xx:3, <EAd> H: Previous value remains unchanged. N: Previous value remains unchanged. Operand Size Z: Previous value remains unchanged.

  • Page 68: Bixor

    2.2.13 BIXOR BIXOR (Bit Invert eXclusive OR) Bit Exclusive Logical OR Operation Condition Code C ⊕ [¬ (<bit No.> of <EAd>)] → C UI H — — — — — — — Assembly-Language Format BIXOR #xx:3, <EAd> H: Previous value remains unchanged. N: Previous value remains unchanged.

  • Page 69: Bld

    2.2.14 BLD BLD (Bit LoaD) Bit Load Operation Condition Code (<Bit No.> of <EAd>) → C UI H — — — — — — — Assembly-Language Format BLD #xx:3, <EAd> H: Previous value remains unchanged. N: Previous value remains unchanged. Operand Size Z: Previous value remains unchanged.

  • Page 70: Bnot

    2.2.15 BNOT BNOT (Bit NOT) Bit NOT Operation Condition Code ¬ (<bit No.> of <EAd>) → (<bit No.> of UI H <EAd>) — — — — — — — — Assembly-Language Format H: Previous value remains unchanged. BNOT #xx:3, <EAd> N: Previous value remains unchanged.
  • Page 71 BNOT (Bit NOT) Bit NOT Operand Format and Number of States Required for Execution Instruction Format Addressing No. of Mnemonic Operands Mode* States 1st byte 2nd byte 3rd byte 4th byte Register direct BNOT #xx:3, Rd 0 IMM Register indirect BNOT #xx:3, @ERd 0 erd...

  • Page 72: Bor

    2.2.16 BOR BOR (bit inclusive OR) Bit Logical OR Operation Condition Code C ∨ [(<bit No.> of <EAd>)] → C UI H — — — — — — — Assembly-Language Format BOR #xx:3, <EAd> H: Previous value remains unchanged. N: Previous value remains unchanged. Operand Size Z: Previous value remains unchanged.

  • Page 73: Bset

    2.2.17 BSET BSET (Bit SET) Bit Set Operation Condition Code 1 → (<bit No.> of <EAd>) UI H — — — — — — — — Assembly-Language Format BSET #xx:3, <EAd> H: Previous value remains unchanged. BSET Rn, <EAd> N: Previous value remains unchanged. Z: Previous value remains unchanged.
  • Page 74 BSET (Bit SET) Bit Set Operand Format and Number of States Required for Execution Instruction Format Addressing No. of Mnemonic Operands Mode* States 1st byte 2nd byte 3rd byte 4th byte Register direct BSET #xx:3, Rd 0 IMM Register indirect BSET #xx:3, @ERd 0 erd...

  • Page 75: Bsr

    2.2.18 BSR BSR (Branch to SubRoutine) Branch to Subroutine Operation Condition Code PC → @–SP UI H PC + disp → PC — — — — — — — — Assembly-Language Format H: Previous value remains unchanged. BSR disp N: Previous value remains unchanged. Z: Previous value remains unchanged.

  • Page 76: Bst

    2.2.19 BST BST (Bit STore) Bit Store Operation Condition Code C → (<bit No.> of <EAd>) UI H — — — — — — — — Assembly-Language Format BST #xx:3, <EAd> H: Previous value remains unchanged. N: Previous value remains unchanged. Operand Size Z: Previous value remains unchanged.

  • Page 77: Btst

    2.2.20 BTST BTST (Bit TeST) Bit Test Operation Condition Code ¬ (<Bit No.> of <EAd>) → Z UI H — — — — — — — Assembly-Language Format BTST #xx:3, <EAd> H: Previous value remains unchanged. BTST Rn, <EAd> N: Previous value remains unchanged. Z: Set to 1 if the specified bit is zero;...
  • Page 78 BTST (Bit TeST) Bit Test Operand Format and Number of States Required for Execution Instruction Format Addressing No. of Mnemonic Operands Mode* States 1st byte 2nd byte 3rd byte 4th byte Register direct BTST #xx:3, Rd 0 IMM Register indirect BTST #xx:3, @ERd 0 erd...

  • Page 79: Bxor

    2.2.21 BXOR BXOR (Bit eXclusive OR) Bit Exclusive Logical OR Operation Condition Code C ⊕ (<bit No.> of <EAd>) → C UI H — — — — — — — Assembly-Language Format BXOR #xx:3, <EAd> H: Previous value remains unchanged. N: Previous value remains unchanged.

  • Page 80: 1) Cmp (B)

    2.2.22 (1) CMP (B) CMP (CoMPare) Compare Operation Condition Code Rd – (EAs), set or clear CCR UI H — — — Assembly-Language Format CMP.B <EAs>, Rd H: Set to 1 if there is a borrow at bit 3; otherwise cleared to 0. Operand Size N: Set to 1 if the result is negative;...

  • Page 81: 2) Cmp (W)

    2.2.22 (2) CMP (W) CMP (CoMPare) Compare Operation Condition Code Rd – (EAs), set CCR UI H — — — Assembly-Language Format CMP.W <EAs>, Rd H: Set to 1 if there is a borrow at bit 11; otherwise cleared to 0. Operand Size N: Set to 1 if the result is negative;...

  • Page 82: 3) Cmp (L)

    2.2.22 (3) CMP (L) CMP (CoMPare) Compare Operation Condition Code ERd – (EAs), set CCR — — — Assembly-Language Format CMP.L <EAs>, ERd Previous value remains unchanged. H: Set to 1 if there is a borrow at bit 27; Operand Size otherwise cleared to 0.

  • Page 83: Daa

    2.2.23 DAA DAA (Decimal Adjust Add) Decimal Adjust Operation Condition Code Rd (decimal adjust) → Rd UI H — — — Assembly-Language Format DAA Rd H: Undetermined (no guaranteed value). N: Set to 1 if the adjusted result is negative; Operand Size otherwise cleared to 0.
  • Page 84 DAA (Decimal Adjust Add) Decimal Adjust Available Registers Rd: R0L to R7L, R0H to R7H Operand Format and Number of States Required for Execution Instruction Format Addressing No. of Mnemonic Operands Mode States 1st byte 2nd byte 3rd byte 4th byte Register direct Notes Valid results (8-bit register Rd contents and C, V, Z, N, and H flags) are not assured if this...

  • Page 85: Das

    2.2.24 DAS DAS (Decimal Adjust Subtract) Decimal Adjust Operation Condition Code Rd (decimal adjust) → Rd UI H — — — — Assembly-Language Format DAS Rd H: Undetermined (no guaranteed value). N: Set to 1 if the adjusted result is negative; Operand Size otherwise cleared to 0.
  • Page 86 DAS (Decimal Adjust Subtract) Decimal Adjust Operand Format and Number of States Required for Execution Instruction Format Addressing No. of Mnemonic Operands Mode States 1st byte 2nd byte 3rd byte 4th byte Register direct Notes Valid results (8-bit register Rd contents and C, V, Z, N, and H flags) are not assured if this instruction is executed under conditions other than those described above.

  • Page 87: 1) Dec (B)

    2.2.25 (1) DEC (B) DEC (DECrement) Decrement Operation Condition Code Rd – 1 → Rd UI H — — — — — Assembly-Language Format DEC.B Rd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise Operand Size cleared to 0.

  • Page 88: 2) Dec (W)

    2.2.25 (2) DEC (W) DEC (DECrement) Decrement Operation Condition Code Rd – 1 → Rd UI H Rd – 2 → Rd — — — — — Assembly-Language Format H: Previous value remains unchanged. DEC.W #1, Rd N: Set to 1 if the result is negative; otherwise DEC.W #2, Rd cleared to 0.

  • Page 89: 3) Dec (L)

    2.2.25 (3) DEC (L) DEC (DECrement) Decrement Operation Condition Code ERd – 1 → ERd UI H ERd – 2 → ERd — — — — — Assembly-Language Format H: Previous value remains unchanged. DEC.L #1, ERd N: Set to 1 if the result is negative; otherwise DEC.L #2, ERd cleared to 0.

  • Page 90: 1) Divxs (B)

    2.2.26 (1) DIVXS (B) DIVXS (DIVide eXtend as Signed) Divide Signed Operation Condition Code Rd ÷ Rs → Rd UI H — — — — — — Assembly-Language Format DIVXS.B Rs, Rd H: Previous value remains unchanged. N: Set to 1 if the quotient is negative; Operand Size otherwise cleared to 0.
  • Page 91 DIVXS (B) DIVXS (DIVide eXtend as Signed) Divide Signed Operand Format and Number of States Required for Execution Instruction Format Addressing No. of Mnemonic Operands Mode States 1st byte 2nd byte 3rd byte 4th byte Register direct DIVXS.B Rs, Rd Notes The N flag is set to 1 if the dividend and divisor have different signs, and cleared to 0 if they have the same sign.

  • Page 92: 2) Divxs (W)

    2.2.26 (2) DIVXS (W) DIVXS (DIVide eXtend as Signed) Divide Signed Operation Condition Code ERd ÷ Rs → ERd UI H — — — — — — Assembly-Language Format DIVXS.W Rs, ERd H: Previous value remains unchanged. N: Set to 1 if the quotient is negative; Operand Size otherwise cleared to 0.
  • Page 93 DIVXS (W) DIVXS (DIVide eXtend as Signed) Divide Signed Operand Format and Number of States Required for Execution Instruction Format Addressing No. of Mnemonic Operands Mode States 1st byte 2nd byte 3rd byte 4th byte Register direct DIVXS.W Rs, ERd 0 erd Notes The N flag is set to 1 if the dividend and divisor have different signs, and cleared to 0 if they have...

  • Page 94: 3) Divxs

    2.2.26 (3) DIVXS DIVXS (DIVide eXtend as Signed) Divide Signed DIVXS instruction, Division by Zero, and Overflow Since the DIVXS instruction does not detect division by zero or overflow, applications should detect and handle division by zero and overflow using techniques similar to those used in the following program.
  • Page 95 DIVXS DIVXS (DIVide eXtend as Signed) Divide Signed Example 2: Sign extend the 8-bit divisor to 16 bits, sign extend the 16-bit dividend to 32 bits, and then use DIVXS to divide EXTS.W ZERODIV EXTS.L DIVXS.L R0,ER1 ZERODIV: This program leaves the 16-bit quotient in R1 and the 8-bit remainder in E1 (in a 16-bit sign extended format).
  • Page 96 DIVXS DIVXS (DIVide eXtend as Signed) Divide Signed 2. Programming solution for DIVXS.W R0, ER1 Example: Convert dividend and divisor to non-negative numbers, then use DIVXU programming solution for zero divide and overflow MOV.W R0, R0 ; Test divisor ZERODIV ;...
  • Page 97 DIVXS (W) DIVXS (DIVide eXtend as Signed) Divide Signed The preceding two examples flag the status of the divisor and dividend in the UI and U bits in the CCR, and modify the sign of the quotient and remainder in the unsigned division result of the DIVXU instruction as shown next.

  • Page 98: 1) Divxu (B)

    2.2.27 (1) DIVXU (B) DIVXU (DIVide eXtend as Unsigned) Divide Operation Condition Code Rd ÷ Rs → Rd UI H — — — — — — Assembly-Language Format DIVXU.B Rs, Rd H: Previous value remains unchanged. N: Set to 1 if the divisor is negative; Operand Size otherwise cleared to 0.

  • Page 99: 2) Divxu (W)

    2.2.27 (2) DIVXU (W) DIVXU (DIVide eXtend as Unsigned) Divide Operation Condition Code ERd ÷ Rs → ERd UI H — — — — — — Assembly-Language Format DIVXU.W Rs, ERd H: Previous value remains unchanged. N: Set to 1 if the divisor is negative; Operand Size otherwise cleared to 0.
  • Page 100 DIVXU DIVXU (DIVide eXtend as Unsigned) Divide DIVXU Instruction, Zero Divide, and Overflow Zero divide and overflow are not detected in the DIVXU instruction. A program like the following can detect zero divisors and avoid overflow. 1. Programming solutions for DIVXU.B R0L, R1 Example 1: Divide upper 8 bits and lower 8 bits of 16-bit dividend separately and obtain 16-bit quotient CMP.B...
  • Page 101 DIVXU DIVXU (DIVide eXtend as Unsigned) Divide Example 2: Zero-extend divisor from 8 to 16 bits and dividend from 16 to 32 bits before dividing EXTU.W ; Zero-extend 8-bit divisor to 16 bits ZERODIV ; Branch to ZERODIV if R0 = 0 EXTU.L ;...
  • Page 102 DIVXU DIVXU (DIVide eXtend as Unsigned) Divide 2. Programming solution for DIVXU.W R0, ER1 Example 1: Divide upper 16 bits and lower 16 bits of 32-bit dividend separately and obtain 32-bit quotient ; R0 = 0? (Zero divisor?) MOV.W R0, R0 ZERODIV ;...

  • Page 103: 1) Eepmov (B)

    2.2.28 (1) EEPMOV (B) EEPMOV (MOVe data to EEPROM) Block Data Transfer Operation Condition Code if R4L ≠ 0 then UI H @ER5+ → @ER6+ repeat — — — — — — — — R4L – 1 → R4L until R4L = 0 H: Previous value remains unchanged.

  • Page 104: 2) Eepmov (W)

    2.2.28 (2) EEPMOV (W) EEPMOV (MOVe data to EEPROM) Block Data Transfer Operation Condition Code if R4 ≠ 0 then UI H @ER5+ → @ER6+ repeat — — — — — — — — R4 – 1 → R4 until R4 = 0 H: Previous value remains unchanged.
  • Page 105 EEPMOV (W) EEPMOV (MOVe data to EEPROM) Block Data Transfer EEPMOV.W Instruction and NMI Interrupt If an NMI request occurs while the EEPMOV.W instruction is being executed, NMI interrupt exception handling is carried out at the end of the current read-write cycle. Register contents are then as follows: ER5: address of the next byte to be transferred ER6: destination address of the next byte...

  • Page 106: 1) Exts (W)

    2.2.29 (1) EXTS (W) EXTS (EXTend as Signed) Sign Extension Operation Condition Code (<Bit 7> of Rd) → (<bits 15 to 8> of Rd> UI H — — — — — Assembly-Language Format EXTS.W Rd H: Previous value remains unchanged. N: Set to 1 if the result is negative;...

  • Page 107: 2) Exts (L)

    2.2.29 (2) EXTS (L) EXTS (EXTend as Signed) Sign Extension Operation Condition Code (<Bit 15> of ERd) → (<bits 31 to 16> of ERd>) UI H — — — — — Assembly-Language Format EXTS.L ERd Previous value remains unchanged. H: Previous value remains unchanged. Operand Size N: Set to 1 if the result is negative;...

  • Page 108: 1) Extu (W)

    2.2.30 (1) EXTU (W) EXTU (EXTend as Unsigned) Zero Extension Operation Condition Code 0 → (<bits 15 to 8> of Rd>) UI H Zero extend — — — — — Assembly-Language Format H: Previous value remains unchanged. EXTU.W Rd N: Always cleared to 0. Z: Set to 1 if the result is zero;...

  • Page 109: 2) Extu (L)

    2.2.30 (2) EXTU (L) EXTU (EXTend as Unsigned) Zero Extension Operation Condition Code 0 → (<bits 31 to 16> of ERd>) UI H Zero extend — — — — — Assembly-Language Format H: Previous value remains unchanged. EXTU.L ERd N: Always cleared to 0. Z: Set to 1 if the result is zero;...

  • Page 110: 1) Inc (B)

    2.2.31 (1) INC (B) INC (INCrement) Increment Operation Condition Code Rd + 1 → Rd UI H — — — — — Assembly-Language Format INC.B Rd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise Operand Size cleared to 0.

  • Page 111: 2) Inc (W)

    2.2.31 (2) INC (W) INC (INCrement) Increment Operation Condition Code Rd + 1 → Rd UI H Rd + 2 → Rd — — — — — Assembly-Language Format H: Previous value remains unchanged. INC.W #1, Rd N: Set to 1 if the result is negative; otherwise INC.W #2, Rd cleared to 0.

  • Page 112: 3) Inc (L)

    2.2.31 (3) INC (L) INC (INCrement) Increment Operation Condition Code ERd + 1 → ERd UI H ERd + 2 → ERd — — — — — Assembly-Language Format H: Previous value remains unchanged. INC.L #1, ERd N: Set to 1 if the result is negative; otherwise INC.L #2, ERd cleared to 0.

  • Page 113: Jmp

    2.2.32 JMP JMP (JuMP) Unconditional Branch Operation Condition Code Effective address → PC UI H — — — — — — — — Assembly-Language Format JMP <EA> H: Previous value remains unchanged. N: Previous value remains unchanged. Operand Size Z: Previous value remains unchanged. —...

  • Page 114: Jsr

    2.2.33 JSR JSR (Jump to SubRoutine) Jump to Subroutine Operation Condition Code PC → @–SP UI H Effective address → PC — — — — — — — — Assembly-Language Format H: Previous value remains unchanged. JSR <EA> N: Previous value remains unchanged. Z: Previous value remains unchanged.
  • Page 115 JSR (Jump to SubRoutine) Jump to Subroutine Notes Note that the structures of the stack and branch addresses differ between normal and advanced mode. Only the lower 16 bits of the PC are saved in normal mode. The branch address must be even. Reserved 16 15 16 15...

  • Page 116: 1) Ldc (B)

    2.2.34 (1) LDC (B) LDC (LoaD to Control register) Load CCR Operation Condition Code (EAs) → CCR UI H Assembly-Language Format LDC.B <EAs>, CCR Loaded from the corresponding bit in the source operand. Operand Size H: Loaded from the corresponding bit in the Byte source operand.

  • Page 117: 2) Ldc (W)

    2.2.34 (2) LDC (W) LDC (LoaD to Control register) Load CCR Operation Condition Code (EAs) → CCR UI H Assembly-Language Format LDC.W <EAs>, CCR Loaded from the corresponding bit in the source operand. Operand Size H: Loaded from the corresponding bit in the Word source operand.
  • Page 118 Operand Format and Number of States Required for Execution Instruction Format No. of Addressing Mnemonic Operands States Mode 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Register LDC.W @ERs,CCR indirect LDC.W...

  • Page 119: 1) Mov (B)

    2.2.35 (1) MOV (B) MOV (MOVe data) Move Operation Condition Code Rs → Rd UI H — — — — — Assembly-Language Format MOV.B Rs, Rd H: Previous value remains unchanged. N: Set to 1 if the data value is negative; Operand Size otherwise cleared to 0.

  • Page 120: 2) Mov (W)

    2.2.35 (2) MOV (W) MOV (MOVe data) Move Operation Condition Code Rs → Rd UI H — — — — — Assembly-Language Format MOV.W Rs, Rd H: Previous value remains unchanged. N: Set to 1 if the data value is negative; Operand Size otherwise cleared to 0.

  • Page 121: 3) Mov (L)

    2.2.35 (3) MOV (L) MOV (MOVe data) Move Operation Condition Code ERs → ERd UI H — — — — — Assembly-Language Format MOV.L ERs, ERd H: Previous value remains unchanged. N: Set to 1 if the data value is negative; Operand Size otherwise cleared to 0.

  • Page 122: 4) Mov (B)

    2.2.35 (4) MOV (B) MOV (MOVe data) Move Operation Condition Code (EAs) → Rd UI H — — — — — Assembly-Language Format MOV.B <EAs>, Rd H: Previous value remains unchanged. N: Set to 1 if the data value is negative; Operand Size otherwise cleared to 0.
  • Page 123 Operand Format and Number of States Required for Execution Instruction Format No. of Addressing Mnemonic Operands States Mode 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte Immediate MOV.B #xx:8,Rd Register MOV.B @ERs,Rd indirect MOV.B @(d:16,ERs),Rd...

  • Page 124: 5) Mov (W)

    2.2.35 (5) MOV (W) MOV (MOVe data) Move Operation Condition Code (EAs) → Rd UI H — — — — — Assembly-Language Format MOV.W <EAs>, Rd H: Previous value remains unchanged. N: Set to 1 if the data value is negative; Operand Size otherwise cleared to 0.
  • Page 125 Operand Format and Number of States Required for Execution Instruction Format No. of Addressing Mnemonic Operands States Mode 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte Immediate MOV.W #xx:16,Rd Register MOV.W @ERs,Rd indirect MOV.W @(d:16,ERs),Rd...

  • Page 126: 6) Mov (L)

    2.2.35 (6) MOV (L) MOV (MOVe data) Move Operation Condition Code (EAs) → ERd UI H — — — — — Assembly-Language Format MOV.L <EAs>, ERd H: Previous value remains unchanged. N: Set to 1 if the data value is negative; Operand Size otherwise cleared to 0.
  • Page 127 Operand Format and Number of States Required for Execution Instruction Format No. of Addressing Mnemonic Operands States Mode 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Immediate MOV.L #xx:32,Rd Register MOV.L...

  • Page 128: 7) Mov (B)

    2.2.35 (7) MOV (B) MOV (MOVe data) Move Operation Condition Code Rs → (EAd) UI H — — — — — Assembly-Language Format MOV.B Rs, <EAd> H: Previous value remains unchanged. N: Set to 1 if the data value is negative; Operand Size otherwise cleared to 0.
  • Page 129 Operand Format and Number of States Required for Execution Instruction Format No. of Addressing Mnemonic Operands States Mode 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte Register MOV.B Rs,@ERd indirect MOV.B Rs,@(d:16,ERd) disp Register indirect with...

  • Page 130: 8) Mov (W)

    2.2.35 (8) MOV (W) MOV (MOVe data) Move Operation Condition Code Rs → (EAd) UI H — — — — — Assembly-Language Format MOV.W Rs, <EAd> H: Previous value remains unchanged. N: Set to 1 if the data value is negative; Operand Size otherwise cleared to 0.
  • Page 131 5(8) Operand Format and Number of States Required for Execution Instruction Format No. of Addressing Mnemonic Operands States Mode 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte Register MOV.W Rs,@ERd indirect MOV.W Rs,@(d:16,ERd) disp Register...

  • Page 132: 9) Mov (L)

    2.2.35 (9) MOV (L) MOV (MOVe data) Move Operation Condition Code ERs → (EAd) UI H — — — — — Assembly-Language Format MOV.L ERs, <EAd> H: Previous value remains unchanged. N: Set to 1 if the data value is negative; Operand Size otherwise cleared to 0.
  • Page 133 Operand Format and Number of States Required for Execution Instruction Format No. of Addressing Mnemonic Operands States Mode 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Register MOV.L ERs,@ERd indirect MOV.L...

  • Page 134: Movfpe

    2.2.36 MOVFPE MOVFPE (MOVe From Peripheral with E clock) Move Data with E Clock Operation Condition Code (EAs) → Rd UI H Synchronized with E clock — — — — — Assembly-Language Format H: Previous value remains unchanged. MOVFPE @aa:16, Rd N: Set to 1 if the data value is negative;...

  • Page 135: Movtpe

    2.2.37 MOVTPE MOVTPE (MOVe To Peripheral with E clock) Move Data with E Clock Operation Condition Code Rs → (EAd) UI H Synchronized with E clock — — — — — Assembly-Language Format H: Previous value remains unchanged. MOVTPE Rs, @aa:16 N: Set to 1 if the data value is negative;...

  • Page 136: 1) Mulxs (B)

    2.2.38 (1) MULXS (B) MULXS (MULtiply eXtend as Signed) Multiply Signed Operation Condition Code Rd × Rs → Rd UI H — — — — — — Assembly-Language Format MULXS.B Rs, Rd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise Operand Size cleared to 0.

  • Page 137: 2) Mulxs (W)

    2.2.38 (2) MULXS (W) MULXS (MULtiply eXtend as Signed) Multiply Signed Operation Condition Code ERd × Rs → ERd UI H — — — — — — Assembly-Language Format MULXS.W Rs, ERd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise Operand Size cleared to 0.

  • Page 138: 1) Mulxu (B)

    2.2.39 (1) MULXU (B) MULXU (MULtiply eXtend as Unsigned) Multiply Operation Condition Code Rd × Rs → Rd UI H — — — — — — — — Assembly-Language Format MULXU.B Rs, Rd H: Previous value remains unchanged. N: Previous value remains unchanged. Operand Size Z: Previous value remains unchanged.

  • Page 139: 2) Mulxu (W)

    2.2.39 (2) MULXU (W) MULXU (MULtiply eXtend as Unsigned) Multiply Operation Condition Code ERd × Rs → ERd UI H — — — — — — — — Assembly-Language Format MULXU.W Rs, ERd H: Previous value remains unchanged. N: Previous value remains unchanged. Operand Size Z: Previous value remains unchanged.

  • Page 140: 1) Neg (B)

    2.2.40 (1) NEG (B) NEG (NEGate) Negate Binary Signed Operation Condition Code 0 – Rd → Rd UI H — — — Assembly-Language Format NEG.B Rd H: Set to 1 if there is a borrow at bit 3; otherwise cleared to 0. Operand Size N: Set to 1 if the result is negative;...

  • Page 141: 2) Neg (W)

    2.2.40 (2) NEG (W) NEG (NEGate) Negate Binary Signed Operation Condition Code 0 – Rd → Rd UI H — — — Assembly-Language Format NEG.W Rd H: Set to 1 if there is a borrow at bit 11; otherwise cleared to 0. Operand Size N: Set to 1 if the result is negative;...

  • Page 142: 3) Neg (L)

    2.2.40 (3) NEG (L) NEG (NEGate) Negate Binary Signed Operation Condition Code 0 – ERd → ERd UI H — — — Assembly-Language Format NEG.L ERd H: Set to 1 if there is a borrow at bit 27; otherwise cleared to 0. Operand Size N: Set to 1 if the result is negative;...

  • Page 143: Nop

    2.2.41 NOP NOP (No OPeration) No Operation Operation Condition Code PC + 2 → PC UI H — — — — — — — — Assembly-Language Format H: Previous value remains unchanged. Operand Size N: Previous value remains unchanged. — Z: Previous value remains unchanged.

  • Page 144: 1) Not (B)

    2.2.42 (1) NOT (B) NOT (NOT = logical complement) Logical Complement Operation Condition Code ¬ Rd → Rd UI H — — — — — Assembly-Language Format NOT.B Rd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise Operand Size cleared to 0.

  • Page 145: 2) Not (W)

    2.2.42 (2) NOT (W) NOT (NOT = logical complement) Logical Complement Operation Condition Code ¬ Rd → Rd UI H — — — — — Assembly-Language Format NOT.W Rd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise Operand Size cleared to 0.

  • Page 146: 3) Not (L)

    2.2.42 (3) NOT (L) NOT (NOT = logical complement) Logical Complement Operation Condition Code ¬ ERd → ERd UI H — — — — — Assembly-Language Format NOT.L ERd Previous value remains unchanged. H: Previous value remains unchanged. Operand Size N: Set to 1 if the result is negative;...

  • Page 147: 1) Or (B)

    2.2.43 (1) OR (B) OR (inclusive OR logical) Logical OR Operation Condition Code Rd ∨ (EAs) → Rd UI H — — — — — Assembly-Language Format OR.B <EAs>, Rd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise Operand Size cleared to 0.

  • Page 148: 2) Or (W)

    2.2.43 (2) OR (W) OR (inclusive OR logical) Logical OR Operation Condition Code Rd ∨ (EAs) → Rd UI H — — — — — Assembly-Language Format OR.W <EAs>, Rd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise Operand Size cleared to 0.

  • Page 149: 3) Or (L)

    2.2.43 (3) OR (L) OR (inclusive OR logical) Logical OR Operation Condition Code ERd ∨ (EAs) → ERd UI H — — — — — Assembly-Language Format OR.L <EAs>, ERd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise Operand Size cleared to 0.

  • Page 150: Orc

    2.2.44 ORC ORC (inclusive OR Control register) Logical OR with CCR Operation Condition Code CCR ∨ #IMM → CCR UI H Assembly-Language Format ORC #xx:8, CCR Stores the corresponding bit of the result. UI: Stores the corresponding bit of the result. Operand Size H: Stores the corresponding bit of the result.

  • Page 151: 1) Pop (W)

    2.2.45 (1) POP (W) POP (POP data) Pop Data from Stack Operation Condition Code @SP+ → Rn UI H — — — — — Assembly-Language Format POP.W Rn H: Previous value remains unchanged. N: Set to 1 if the data value is negative; Operand Size otherwise cleared to 0.

  • Page 152: 2) Pop (L)

    2.2.45 (2) POP (L) POP (POP data) Pop Data from Stack Operation Condition Code @SP+ → ERn UI H — — — — — Assembly-Language Format POP.L ERn H: Previous value remains unchanged. N: Set to 1 if the data value is negative; Operand Size otherwise cleared to 0.

  • Page 153: 1) Push (W)

    2.2.46 (1) PUSH (W) PUSH (PUSH data) Push Data on Stack Operation Condition Code Rn → @–SP UI H — — — — — Assembly-Language Format PUSH.W Rn H: Previous value remains unchanged. N: Set to 1 if the data value is negative; Operand Size otherwise cleared to 0.

  • Page 154: 2) Push (L)

    2.2.46 (2) PUSH (L) PUSH (PUSH data) Push Data on Stack Operation Condition Code ERn → @–SP UI H — — — — — Assembly-Language Format PUSH.L ERn H: Previous value remains unchanged. N: Set to 1 if the data value is negative; Operand Size otherwise cleared to 0.

  • Page 155: 1) Rotl (B)

    2.2.47 (1) ROTL (B) ROTL (ROTate Left) Rotate Operation Condition Code Rd (left rotation) → Rd UI H — — — — Assembly-Language Format ROTL.B Rd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise Operand Size cleared to 0.

  • Page 156: 2) Rotl (W)

    2.2.47 (2) ROTL (W) ROTL (ROTate Left) Rotate Operation Condition Code Rd (left rotation) → Rd UI H — — — — Assembly-Language Format ROTL.W Rd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise Operand Size cleared to 0.

  • Page 157: 3) Rotl (L)

    2.2.47 (3) ROTL (L) ROTL (ROTate Left) Rotate Operation Condition Code ERd (left rotation) → ERd UI H — — — — — Assembly-Language Format ROTL.L ERd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise Operand Size cleared to 0.

  • Page 158: 1) Rotr (B)

    2.2.48 (1) ROTR (B) ROTR (ROTate Right) Rotate Operation Condition Code Rd (right rotation) → Rd UI H — — — — Assembly-Language Format ROTR.B Rd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise Operand Size cleared to 0.

  • Page 159: 2) Rotr (W)

    2.2.48 (2) ROTR (W) ROTR (ROTate Right) Rotate Operation Condition Code Rd (right rotation) → Rd UI H — — — — Assembly-Language Format ROTR.W Rd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise Operand Size cleared to 0.

  • Page 160: 3) Rotr (L)

    2.2.48 (3) ROTR (L) ROTR (ROTate Right) Rotate Operation Condition Code ERd (right rotation) → ERd UI H — — — — Assembly-Language Format ROTR.L ERd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise Operand Size cleared to 0.

  • Page 161: 1) Rotxl (B)

    2.2.49 (1) ROTXL (B) ROTXL (ROTate with eXtend carry Left) Rotate through Carry Operation Condition Code Rd (left rotation through carry bit) → Rd UI H — — — — Assembly-Language Format ROTXL.B Rd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise Operand Size cleared to 0.

  • Page 162: 2) Rotxl (W)

    2.2.49 (2) ROTXL (W) ROTXL (ROTate with eXtend carry Left) Rotate through Carry Operation Condition Code Rd (left rotation through carry bit) → Rd UI H — — — — Assembly-Language Format ROTXL.W Rd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise Operand Size cleared to 0.

  • Page 163: 3) Rotxl (L)

    2.2.49 (3) ROTXL (L) ROTXL (ROTate with eXtend carry Left) Rotate through Carry Operation Condition Code ERd (left rotation through carry bit) → ERd UI H — — — — Assembly-Language Format ROTXL.L ERd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise Operand Size cleared to 0.

  • Page 164: 1) Rotxr (B)

    2.2.50 (1) ROTXR (B) ROTXR (ROTate with eXtend carry Right) Rotate through Carry Operation Condition Code Rd (right rotation through carry bit) → Rd UI H — — — — Assembly-Language Format ROTXR.B Rd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise Operand Size cleared to 0.

  • Page 165: 2) Rotxr (W)

    2.2.50 (2) ROTXR (W) ROTXR (ROTate with eXtend carry Right) Rotate through Carry Operation Condition Code Rd (right rotation through carry bit) → Rd UI H — — — — Assembly-Language Format ROTXR.W Rd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise Operand Size cleared to 0.

  • Page 166: 3) Rotxr (L)

    2.2.50 (3) ROTXR (L) ROTXR (ROTate with eXtend carry Right) Rotate through Carry Operation Condition Code ERd (right rotation through carry bit) → ERd UI H — — — — Assembly-Language Format ROTXR.L ERd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise Operand Size cleared to 0.

  • Page 167: Rte

    2.2.51 RTE RTE (ReTurn from Exception) Return from Exception Handling Operation Condition Code @SP+ → CCR UI H @SP+ → PC Assembly-Language Format Restored from the corresponding bit on the stack. UI: Restored from the corresponding bit on the stack. Operand Size H: Restored from the corresponding bit on the stack.

  • Page 168: Rts

    2.2.52 RTS RTS (ReTurn from Subroutine) Return from Subroutine Operation Condition Code @SP+ → PC UI H — — — — — — — — Assembly-Language Format H: Previous value remains unchanged. N: Previous value remains unchanged. Operand Size Z: Previous value remains unchanged. —...

  • Page 169: 1) Shal (B)

    2.2.53 (1) SHAL (B) SHAL (SHift Arithmetic Left) Shift Arithmetic Operation Condition Code Rd (left arithmetic shift) → Rd UI H — — — — Assembly-Language Format SHAL.B Rd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise Operand Size cleared to 0.

  • Page 170: 2) Shal (W)

    2.2.53 (2) SHAL (W) SHAL (SHift Arithmetic Left) Shift Arithmetic Operation Condition Code Rd (left arithmetic shift) → Rd UI H — — — — Assembly-Language Format SHAL.W Rd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise Operand Size cleared to 0.

  • Page 171: 3) Shal (L)

    2.2.53 (3) SHAL (L) SHAL (SHift Arithmetic Left) Shift Arithmetic Operation Condition Code ERd (left arithmetic shift) → ERd UI H — — — — Assembly-Language Format SHAL.L ERd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise Operand Size cleared to 0.

  • Page 172: 1) Shar (B)

    2.2.54 (1) SHAR (B) SHAR (SHift Arithmetic Right) Shift Arithmetic Operation Condition Code Rd (right arithmetic shift) → Rd UI H — — — — Assembly-Language Format SHAR.B Rd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise Operand Size cleared to 0.

  • Page 173: 2) Shar (W)

    2.2.54 (2) SHAR (W) SHAR (SHift Arithmetic Right) Shift Arithmetic Operation Condition Code Rd (right arithmetic shift) → Rd UI H — — — — — Assembly-Language Format SHAR.W Rd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise Operand Size cleared to 0.

  • Page 174: 3) Shar (L)

    2.2.54 (3) SHAR (L) SHAR (SHift Arithmetic Right) Shift Arithmetic Operation Condition Code ERd (right arithmetic shift) → ERd UI H — — — — Assembly-Language Format SHAR.L ERd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise Operand Size cleared to 0.

  • Page 175: 1) Shll (B)

    2.2.55 (1) SHLL (B) SHLL (SHift Logical Left) Shift Logical Operation Condition Code Rd (left logical shift) → Rd UI H — — — — — Assembly-Language Format SHLL.B Rd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise Operand Size cleared to 0.

  • Page 176: 2) Shll (W)

    2.2.55 (2) SHLL (W) SHLL (SHift Logical Left) Shift Logical Operation Condition Code Rd (left logical shift) → Rd UI H — — — — Assembly-Language Format SHLL.W Rd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise Operand Size cleared to 0.

  • Page 177: 3) Shll (L)

    2.2.55 (3) SHLL (L) SHLL (SHift Logical Left) Shift Logical Operation Condition Code ERd (left logical shift) → ERd UI H — — — — Assembly-Language Format SHLL.L ERd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise Operand Size cleared to 0.

  • Page 178: 1) Shlr (B)

    2.2.56 (1) SHLR (B) SHLR (SHift Logical Right) Shift Logical Operation Condition Code Rd (right logical shift) → Rd UI H — — — — Assembly-Language Format SHLR.B Rd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise Operand Size cleared to 0.

  • Page 179: 2) Shlr (W)

    2.2.56 (2) SHLR (W) SHLR (SHift Logical Right) Shift Logical Operation Condition Code Rd (right logical shift) → Rd UI H — — — — Assembly-Language Format SHLR.W Rd H: Previous value remains unchanged. N: Always cleared to 0. Operand Size Z: Set to 1 if the result is zero;...

  • Page 180: 3) Shlr (L)

    2.2.56 (3) SHLR (L) SHLR (SHift Logical Right) Shift Logical Operation Condition Code ERd (right logical shift) → ERd UI H — — — — Assembly-Language Format SHLR.L ERd H: Previous value remains unchanged. N: Always cleared to 0. Operand Size Z: Set to 1 if the result is zero;...

  • Page 181: Sleep

    2.2.57 SLEEP SLEEP (SLEEP) Power-Down Mode Operation Condition Code Program execution state → power-down mode UI H — — — — — — — — Assembly-Language Format SLEEP H: Previous value remains unchanged. N: Previous value remains unchanged. Operand Size Z: Previous value remains unchanged.

  • Page 182: 1) Stc (B)

    2.2.58 (1) STC (B) STC (STore from Control register) Store CCR Operation Condition Code CCR → Rd UI H — — — — — — — — Assembly-Language Format STC.B CCR, Rd H: Previous value remains unchanged. N: Previous value remains unchanged. Operand Size Z: Previous value remains unchanged.

  • Page 183: 2) Stc (W)

    2.2.58 (2) STC (W) STC (STore from Control register) Store CCR Operation Condition Code CCR → (EAd) UI H — — — — — — — — Assembly-Language Format STC.W CCR, <EAd> H: Previous value remains unchanged. N: Previous value remains unchanged. Operand Size Z: Previous value remains unchanged.
  • Page 184 Operand Format and Number of States Required for Execution Instruction Format No. of Addressing Mnemonic Operands States Mode 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Register STC.W CCR,@ERd indirect STC.W...

  • Page 185: 1) Sub (B)

    2.2.59 (1) SUB (B) SUB (SUBtract binary) Subtract Binary Operation Condition Code Rd – Rs → Rd UI H — — — Assembly-Language Format SUB.B Rs, Rd H: Set to 1 if there is a borrow at bit 3; otherwise cleared to 0. Operand Size N: Set to 1 if the result is negative;...

  • Page 186: 2) Sub (W)

    2.2.59 (2) SUB (W) SUB (SUBtract binary) Subtract Binary Operation Condition Code Rd – (EAs) → Rd UI H — — — Assembly-Language Format SUB.W <EAs>, Rd H: Set to 1 if there is a borrow at bit 11; otherwise cleared to 0. Operand Size N: Set to 1 if the result is negative;...

  • Page 187: 3) Sub (L)

    2.2.59 (3) SUB (L) SUB (SUBtract binary) Subtract Binary Operation Condition Code ERd – <EAs> → ERd UI H — — — Assembly-Language Format SUB.L <EAs>, ERd H: Set to 1 if there is a borrow at bit 27; otherwise cleared to 0. Operand Size N: Set to 1 if the result is negative;...

  • Page 188: Subs

    2.2.60 SUBS SUBS (SUBtract with Sign extension) Subtract Binary Address Data Operation Condition Code ERd – 1 → ERd UI H ERd – 2 → ERd — — — — — — — — ERd – 4 → ERd H: Previous value remains unchanged. Assembly-Language Format N: Previous value remains unchanged.

  • Page 189: Subx

    2.2.61 SUBX SUBX (SUBtract with eXtend carry) Subtract with Borrow Operation Condition Code Rd – (EAs) – C → Rd UI H — — — Assembly-Language Format SUBX <EAs>, Rd H: Set to 1 if there is a borrow from bit 3; otherwise cleared to 0.

  • Page 190: Trapa

    2.2.62 TRAPA TRAPA (TRAP Always) Trap Unconditionally Operation Condition Code PC → @–SP UI H CCR → @–SP 1 ∆ — — — — — — <Vector> → PC Always set to 1. Assembly-Language Format U: See notes. TRAPA #x:2 H: Previous value remains unchanged.

  • Page 191: 1) Xor (B)

    2.2.63 (1) XOR (B) XOR (eXclusive OR logical) Exclusive Logical OR Operation Condition Code Rd ⊕ (EAs) → Rd UI H — — — — — Assembly-Language Format XOR.B <EAs>, Rd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise Operand Size cleared to 0.

  • Page 192: 2) Xor (W)

    2.2.63 (2) XOR (W) XOR (eXclusive OR logical) Exclusive Logical OR Operation Condition Code Rd ⊕ (EAs) → Rd UI H — — — — — Assembly-Language Format XOR.W <EAs>, Rd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise Operand Size cleared to 0.

  • Page 193: 3) Xor (L)

    2.2.63 (3) XOR (L) XOR (eXclusive OR logical) Exclusive Logical OR Operation Condition Code ERd ⊕ (EAs) → ERd UI H — — — — — Assembly-Language Format XOR.L <EAs>, ERd H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise Operand Size cleared to 0.

  • Page 194: Xorc

    2.2.64 XORC XORC (eXclusive OR Control register) Exclusive Logical OR with CCR Operation Condition Code CCR ⊕ #IMM → CCR UI H Assembly-Language Format XORC #xx:8, CCR Stores the corresponding bit of the result. UI: Stores the corresponding bit of the result. Operand Size H: Stores the corresponding bit of the result.

  • Page 195: Instruction Set Summary

    2.3 Instruction Set Summary Table 2-1 Instruction Set Summary Addressing Mode Function Instruction #xx @ERn @(d:16,ERn) @(d:24,ERn) @ERn+/@–ERn @aa:8 @aa:16 @aa:24 @(d:8,PC) @(d:16,PC) @@aa:8 — Data BWL BWL — — — — transfer POP, PUSH — — — — — —...
  • Page 196 Table 2-1 Instruction Set Summary (cont) Addressing Mode Function Instruction #xx @ERn @(d:16,ERn) @(d:24,ERn) @ERn+/@–ERn @aa:8 @aa:16 @aa:24 @(d:8,PC) @(d:16,PC) @@aa:8 — Branch Bcc, BSR — — — — — — — — — — — JMP, JSR — — —...
  • Page 197 Table 2-2 Instruction Set (1) Data Transfer Instructions Addressing Mode and Instruction Length (bytes) Condition Code No. of States Mnemonic Size #xx Rn @ERn @(d,ERn) @ERn+/@–ERn @aa @(d,PC) @@aa — Operation N Z V C Normal vanced MOV.B #xx:8,Rd #xx:8→Rd8 —...
  • Page 198 Table 2-2 Instruction Set (cont) (1) Data Transfer Instructions Addressing Mode and Instruction Length (bytes) Condition Code No. of States Mnemonic Size #xx Rn @ERn @(d,ERn) @ERn+/@–ERn @aa @(d,PC) @@aa — Operation N Z V C Normal vanced MOV.L @(d:16,ERs),ERd L @(d:16,ERs)→ERd32 —...
  • Page 199 Table 2-2 Instruction Set (cont) (2) Arithmetic Operation Instructions Addressing Mode and Instruction Length (bytes) Condition Code No. of States Mnemonic Size #xx Rn @ERn @(d,ERn) @ERn+/@–ERn @aa @(d,PC) @@aa — Operation N Z V C Normal vanced ADDS ADDS.L #1,ERd ERd32+1→ERd32 —...
  • Page 200 Table 2-2 Instruction Set (cont) (2) Arithmetic Operation Instructions Addressing Mode and Instruction Length (bytes) Condition Code No. of States Mnemonic Size #xx Rn @ERn @(d,ERn) @ERn+/@–ERn @aa @(d,PC) @@aa — Operation N Z V C Normal vanced CMP.B #xx:8,Rd Rd8–#xx:8 —...
  • Page 201 Table 2-2 Instruction Set (cont) (3) Logic Operation Instructions Addressing Mode and Instruction Length (bytes) Condition Code No. of States Mnemonic Size #xx Rn @ERn @(d,ERn) @ERn+/@–ERn @aa @(d,PC) @@aa — Operation N Z V C Normal vanced Rd8 Λ #xx:8→Rd8 AND.B #xx:8,Rd —...
  • Page 202 Table 2-2 Instruction Set (cont) (4) Shift Instructions Addressing Mode and Instruction Length (bytes) Condition Code No. of States Mnemonic Size #xx Rn @ERn @(d,ERn) @ERn+/@–ERn @aa @(d,PC) @@aa — Operation N Z V C Normal vanced SHAL SHAL.B Rd —...
  • Page 203 Table 2-2 Instruction Set (cont) (5) Bit Manipulation Instructions Addressing Mode and Instruction Length (bytes) Condition Code No. of States Mnemonic Size #xx Rn @ERn @(d,ERn) @ERn+/@–ERn @aa @(d,PC) @@aa — Operation N Z V C Normal vanced BSET BSET #xx:3,Rd (#xx:3 of Rd8)←1 —...
  • Page 204 Table 2-2 Instruction Set (cont) (5) Bit Manipulation Instructions Addressing Mode and Instruction Length (bytes) Condition Code No. of States Mnemonic Size #xx Rn @ERn @(d,ERn) @ERn+/@–ERn @aa @(d,PC) @@aa — Operation N Z V C Normal vanced BST #xx:3,Rd C→(#xx:3 of Rd8) —...
  • Page 205 (6) Branch Instructions Addressing Mode and Instruction Length (bytes) Condition Code No. of States Branch Mnemonic Size #xx Rn @ERn @(d,ERn) @ERn+/@–ERn @aa @(d,PC) @@aa — Operation condition N Z V C Normal vanced BRA d:8(BTd:8) — if condition is true then Always —...
  • Page 206 Table 2-2 Instruction Set (cont) (6) Branch Instructions Addressing Mode and Instruction Length (bytes) Condition Code No. of States Branch Mnemonic Size #xx Rn @ERn @(d,ERn) @ERn+/@–ERn @aa @(d,PC) @@aa — Operation condition N Z V C Normal vanced BSR d:8 —...
  • Page 207 Table 2-2 Instruction Set (cont) (8) Block Transfer Instructions Addressing Mode and Instruction Length (bytes) Condition Code No. of States Mnemonic Size #xx Rn @ERn @(d,ERn) @ERn+/@–ERn @aa @(d,PC) @@aa — Operation N Z V C Normal vanced if R4L ≠ 0 EEPMOV EEPMOV.B —...

  • Page 208: Instruction Codes

    2.4 Instruction Codes Table 2-3 Instruction Codes Instruction Format Instruction Mnemonic Size 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd 0 erd ADD.L ERs,ERd...
  • Page 209 Table 2-3 Instruction Codes (cont) Instruction Format Instruction Mnemonic Size 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte BCS d:16 (BLO d:16) — disp BNE d:8 — disp BNE d:16 —...
  • Page 210 Table 2-3 Instruction Codes (cont) Instruction Format Instruction Mnemonic Size 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte BIOR BIOR #xx:3,Rd 1 IMM BIOR #xx:3,@ERd 0 erd 1 IMM BIOR #xx:3,@aa:8 1 IMM BIST...
  • Page 211 Table 2-3 Instruction Codes (cont) Instruction Format Instruction Mnemonic Size 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte BTST BTST #xx:3,Rd 0 IMM BTST #xx:3,@ERd 0 erd 0 IMM BTST #xx:3,@aa:8 0 IMM BTST Rn,Rd...
  • Page 212 Table 2-3 Instruction Codes (cont) Instruction Format Instruction Mnemonic Size 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte INC.L #1,ERd 0 erd INC.L #2,ERd 0 erd JMP @ERn —...
  • Page 213 Table 2-3 Instruction Codes (cont) Instruction Format Instruction Mnemonic Size 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte MOV.W @(d:16,ERs),Rd 0 ers disp MOV.W @(d:24,ERs),Rd 0 ers disp MOV.W @ERs+,Rd 0 ers MOV.W @aa:16,Rd...
  • Page 214 Table 2-3 Instruction Codes (cont) Instruction Format Instruction Mnemonic Size 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte NOT.B Rd NOT.W Rd NOT.L ERd 0 erd OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd...
  • Page 215 Table 2-3 Instruction Codes (cont) Instruction Format Instruction Mnemonic Size 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte SHLL SHLL.B Rd SHLL.W Rd SHLL.L ERd 0 erd SHLR SHLR.B Rd SHLR.W Rd SHLR.L ERd...
  • Page 216 Legend IMM: Immediate data (2, 3, 8, 16, or 32 bits) abs: Absolute address (8, 16, or 24 bits) disp: Displacement (8, 16, or 24 bits) rs, rd, rn: Register field (4 bits specifying an 8-bit or 16-bit register. rs corresponds to operand symbols such as Rs, rd corresponds to operand symbols such as Rd, and rn corresponds to the operand symbol Rn.) ers, erd, ern: Register field (3 bits specifying a 32-bit register.

  • Page 217: Operation Code Map

    2.5 Operation Code Map Tables 2-4 to 2-6 show an operation code map. Table 2-4 Operation Code Map (1) Operation Code: Instruction when most significant bit of BH is 0. 1st byte 2nd byte Instruction when most significant bit of BH is 1. Table 2-5 XORG ANDC...
  • Page 218 Table 2-5 Operation Code Map (2) Operation Code: 1st byte 2nd byte AH AL SLEEP Table 2-6 Table 2-6 Table 2-6 ADDS ADDS ADDS SHLL SHLL SHAL SHAL SHLR SHLR SHAR SHAR ROTXL ROTXL ROTL ROTL ROTXR ROTXR ROTR ROTR EXTU EXTU EXTS...
  • Page 219 Table 2-6 Operation Code Map (3) Operation Code: 1st byte 2nd byte 3rd byte 4th byte Instruction when most significant bit of DH is 0. Instruction when most significant bit of DH is 1. AHALBHBLCH 01C05 MULXS MULXS 01D05 DIVXS DIVXS 01F06 7Cr06...

  • Page 220: Number Of States Required For Instruction Execution

    2.6 Number of States Required for Instruction Execution The tables in this section can be used to calculate the number of states required for instruction execution by the H8/300H CPU. Table 2-8 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. Table 2-7 indicates the number of states required for each size.
  • Page 221 Table 2-7 Number of States per Cycle Access Conditions External Device On-Chip Supporting Module 8-Bit Bus 16-Bit Bus On-Chip 8-Bit 16-Bit 2-State 3-State 2-State 3-State Cycle Memory Access Access Access Access Instruction fetch 6 + 2 m 3 + m* Branch address read S Stack operation Byte data access...
  • Page 222 Table 2-8 Number of Cycles in Instruction Execution Branch Instruction Address Stack Byte Data Word Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS ADDS #1/2/4,ERd ADDX ADDX #xx:8,Rd ADDX Rs,Rd...
  • Page 223 Table 2-8 Number of Cycles in Instruction Execution (cont) Branch Instruction Address Stack Byte Data Word Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic BCS d:16 (BLO d:16) BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16...
  • Page 224 Table 2-8 Number of Cycles in Instruction Execution (cont) Branch Instruction Address Stack Byte Data Word Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic BNOT BNOT Rn,@aa:8 BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BSET BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET Rn,Rd BSET Rn,@ERd...
  • Page 225 Table 2-8 Number of Cycles in Instruction Execution (cont) Branch Instruction Address Stack Byte Data Word Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic DIVXU DIVXU.B Rs,Rd DIVXU.W Rs,ERd EEPMOV EEPMOV.B 2n + 2 * EEPMOV.W 2n + 2 * EXTS EXTS.W Rd EXTS.L ERd...
  • Page 226 Table 2-8 Number of Cycles in Instruction Execution (cont) Branch Instruction Address Stack Byte Data Word Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic MOV.B Rs,@(d:24,ERd) MOV.B Rs,@–ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:24 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:24,ERs),Rd...
  • Page 227 Table 2-8 Number of Cycles in Instruction Execution (cont) Branch Instruction Address Stack Byte Data Word Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic NEG.B Rd NEG.W Rd NEG.L ERd NOT.B Rd NOT.W Rd NOT.L ERd OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd...
  • Page 228 Table 2-8 Number of Cycles in Instruction Execution (cont) Branch Instruction Address Stack Byte Data Word Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic SHLL SHLL.B Rd SHLL.W Rd SHLL.L ERd SHLR SHLR.B Rd SHLR.W Rd SHLR.L ERd SLEEP SLEEP STC CCR,Rd...

  • Page 229: Condition Code Modification

    2.7 Condition Code Modification This section indicates the effect of each CPU instruction on the condition code. The notation used in the table is defined below. 31 for longword operands, 15 for word operands, 7 for byte operands The i-th bit of the source operand The i-th bit of the destination operand The i-th bit of the result : The specified bit in the destination operand...
  • Page 230 Table 2-7 Condition Code Modification Instruction Definition H = S m – 4 · D m – 4 + D m – 4 · / R m – 4 + S m – 4 · / R m – 4 N = R m Z = / R m ·...
  • Page 231 Table 2-7 Condition Code Modification (cont) Instruction Definition N = R m Z = / R m · / R m – 1 · ... · / R 0 C: decimal arithmetic carry N = R m Z = / R m · / R m – 1 · ... · / R 0 C: decimal arithmetic borrow —...
  • Page 232 Table 2-7 Condition Code Modification (cont) Instruction Definition — — — — — — — N = R m Z = / R m · / R m – 1 · ... · / R 0 — — N = R m Z = / R m ·...
  • Page 233 Table 2-7 Condition Code Modification (cont) Instruction Definition SHLR — N = R m Z = / R m · / R m – 1 · ... · / R 0 C = D 0 SLEEP — — — — — —...

  • Page 234: Bus Cycles During Instruction Execution

    2.8 Bus Cycles During Instruction Execution Table 2-8 indicates the bus cycles during instruction execution by the H8/300H CPU. For the number of states per bus cycle, see table 2-7, Number of States per Cycle. How to read the table: Order of bus cycles Instruction Internal operation...
  • Page 235 Figure 2-1 shows timing waveforms for the address bus and the RD and WR (HWR or LWR) signals during execution of the above instruction with an 8-bit bus, using 3-state access with no wait states. ø Address bus High level (HWR or LWR) Internal R:W 2nd...
  • Page 236 Table 2-8 Bus States Instruction ADD.B #xx:8,Rd R:W NEXT ADD.B Rs,Rd R:W NEXT ADD.W #xx:16,Rd R:W 2nd R:W NEXT ADD.W Rs,Rd R:W NEXT ADD.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT ADD.L ERs,ERd R:W NEXT ADDS #1/2/4,ERd R:W NEXT ADDX #xx:8,Rd R:W NEXT ADDX Rs,Rd R:W NEXT...
  • Page 237 Table 2-8 Bus States (cont) Instruction BGE d:8 R:W NEXT R:W EA BLT d:8 R:W NEXT R:W EA BGT d:8 R:W NEXT R:W EA BLE d:8 R:W NEXT R:W EA BRA d:16 (BT d;16) R:W 2nd Internal operation, R:W EA 2 states BRN d:16 (BF d;16) R:W 2nd...
  • Page 238 Table 2-8 Bus States (cont) Instruction BCLR #xx:3,Rd R:W NEXT BCLR #xx:3,@ERd R:W 2nd R:B EA R:W NEXT W:B EA BCLR #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT W:B EA BCLR Rn,Rd R:W NEXT BCLR Rn,@ERd R:W 2nd R:B EA R:W NEXT W:B EA BCLR Rn,@aa:8...
  • Page 239 Table 2-8 Bus States (cont) Instruction BSET Rn,Rd R:W NEXT BSET Rn,@ERd R:W 2nd R:B EA R:W NEXT W:B EA BSET Rn,@aa:8 R:W 2nd R:B EA R:W NEXT W:B EA BRS d:8 Normal R:W NEXT R:W EA W:W Stack Advanced R:W NEXT R:W EA W:W Stack (H)
  • Page 240 Table 2-8 Bus States (cont) Instruction EXTS.W Rd R:W NEXT EXTS.L ERd R:W NEXT EXTU.W Rd R:W NEXT EXTU.L ERd R:W NEXT INC.B Rd R:W NEXT INC.W #1/2,Rd R:W NEXT INC.L #1/2,ERd R:W NEXT JMP @ERn R:W NEXT R:W EA JMP @aa:24 R:W 2nd Internal operation,...
  • Page 241 Table 2-8 Bus States (cont) Instruction MOV.B @ERs+,Rd R:W NEXT Internal operation, R:B EA 2 states MOV.B @aa:8,Rd R:W NEXT R:B EA MOV.B @aa:16,Rd R:W 2nd R:W NEXT R:B EA MOV.B @aa:24,Rd R:W 2nd R:W 3rd R:W NEXT R:B EA MOV.B Rs,@ERd R:W NEXT W:B EA...
  • Page 242 Table 2-8 Bus States (cont) Instruction MOV.L @aa:16,ERd R:W 2nd R:W 3rd R:W NEXT R:W EA R:W EA+2 MOV.L @aa:24,ERd R:W 2nd R:W 3rd R:W 4th R:W NEXT R:W EA R:W EA+2 MOV.L ERs,@ERd R:W 2nd R:W NEXT W:W EA W:W EA+2 MOV.L ERs,@(d:16,ERd) R:W 2nd...
  • Page 243 Table 2-8 Bus States (cont) Instruction PUSH.W Rn R:W NEXT Internal operation, W:W Stack 2 states PUSH.L ERn R:W 2nd R:W NEXT Internal operation, W:W Stack (L) W:W Stack (H) 2 states ROTL.B Rd R:W NEXT ROTL.W Rd R:W NEXT ROTL.L ERd R:W NEXT ROTR.B Rd...
  • Page 244 Table 2-8 Bus States (cont) Instruction STC CCR,@ERd R:W 2nd R:W NEXT W:W EA STC CCR,@(d:16,ERd) R:W 2nd R:W 3rd R:W NEXT W:W EA STC CCR,@(d:24,ERd) R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT W:W EA STC CCR,@–ERd R:W 2nd R:W NEXT Internal operation,...
  • Page 245 Notes: 1. EAs is the contents of ER5. EAd is the contents of R6. 2. EAs is the contents of ER5. EAd is the contents of R6. Both registers are incremented by 1 after execution of the instruction. n is the initial value of R4L or R4. If n = 0, these bus cycles are not executed. 3.

  • Page 246: Processing States

    Section 3 Processing States 3.1 Overview The CPU has five main processing states: the program execution state, exception handling state, power-down state, reset state, and bus-released state. The power-down state includes sleep mode, software standby mode, and hardware standby mode. Figure 3-1 shows a diagram of the processing states.
  • Page 247 End of bus-released state Bus request Program execution state Sleep mode Bus-released state External interrupt Software standby mode Exception-handling state STBY high, RES low Reset state Hardware standby mode Power-down state Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low.

  • Page 248: Types Of Exception Handling And Their Priority

    3.2 Program Execution State In this state the CPU executes program instructions in normal sequence. 3.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from the exception vector table and branches to that address.

  • Page 249: Program Execution State

    3.3.2 Exception-Handling Sequences Reset Exception Handling: Reset exception handling has the highest priority. The reset state is entered when the RES signal goes low. Then, if RES goes high again, reset exception handling starts when the reset condition is satisfied. Refer to the relevant microcontroller hardware manual for details about the reset condition.
  • Page 250 SP – 4 SP (ER7) SP – 3 SP + 1 SP – 2 SP + 2 SP – 1 SP + 3 Stack area Even address SP (ER7) SP + 4 Before exception After exception handling starts Pushed on stack handling ends (a) Stack structure in normal mode SP –...

  • Page 251: Bus-Released State

    3.4 Bus-Released State This is a state in which the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts except for internal operations. For further details, refer to the relevant microcontroller hardware manual.

  • Page 252: Section 4 Basic Timing

    Section 4 Basic Timing 4.1 Overview The CPU is driven by a clock, denoted by the symbol ø. One cycle of the clock is referred to as a “state.” The memory cycle or bus cycle consists of two or three states. Different methods are used to access on-chip memory, on-chip supporting modules, and external devices.
  • Page 253 Bus cycle state state ø Address bus Address High High WR (HWR or LWR) High Data bus high-impedance state Figure 4-2 Pin States during On-Chip Memory Access...
  • Page 254 4.3 On-Chip Supporting Modules The on-chip supporting modules are accessed in three states. The data bus is 8 bits or 16 bits wide. Figure 4-3 shows the access timing for the on-chip supporting modules. Figure 4-4 shows the pin states. Bus cycle state state...

  • Page 255: On-Chip Supporting Modules

    Bus cycle state state state ø Address Address bus High High WR (HWR or LWR) High Data bus high-impedance state Figure 4-4 Pin States during On-Chip Supporting Module Access 4.4 External Data Bus The external data bus is accessed with 8-bit or 16-bit bus width in two or three states. Figure 4-5 shows the read timing for two-state or three-state access.
  • Page 256 Read cycle state state ø Address bus Address Data bus Read data (two-state access) Read cycle state state state ø Address bus Address Data bus Read data (three-state access) Figure 4-5 External Device Access Timing (1) Read Timing...
  • Page 257 Write cycle state state ø Address bus Address (HWR or LWR) Data bus Write data (a) Two-state access Write cycle state state state ø Address bus Address (HWR or LWR) Data bus Write data (b) Three-state access Figure 4-6 External Device Access Timing (2) Write Timing...

Table of Contents