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20.2.3
Module Stop Control Register (MSTPCR)....................................................... 384
20.3 14-Bit PWM Operation..................................................................................................... 385
21.1 Overview........................................................................................................................... 387
21.1.1
Features............................................................................................................. 387
21.1.2
Block Diagram.................................................................................................. 388
21.1.3
Pin Configuration ............................................................................................. 389
21.1.4
Register Configuration...................................................................................... 389
21.2 Registers............................................................................................................................ 390
21.2.1
Input Capture Register 1 (ICR1)....................................................................... 390
21.2.2
Prescalar Unit Control/Status Register (PCSR) ................................................ 390
21.2.3
Port Mode Register 1 (PMR1) .......................................................................... 393
21.3 Noise Cancel Circuit ......................................................................................................... 394
21.4 Operation .......................................................................................................................... 394
21.4.1
Prescalar S (PSS) .............................................................................................. 394
21.4.2
Prescalar W (PSW) ........................................................................................... 395
21.4.3
Stable Oscillation Wait Time Count ................................................................. 395
21.4.4
8-bit PWM ........................................................................................................ 396
8-bit Input Capture Using ,& Pin ...................................................................... 396
21.4.5
21.4.6
Frequency Division Clock Output .................................................................... 396
22.1 Overview........................................................................................................................... 397
22.1.1
Features............................................................................................................. 397
22.1.2
Block Diagram.................................................................................................. 399
22.1.3
Pin Configuration ............................................................................................. 400
22.1.4
Register Configuration...................................................................................... 400
22.2 Register Descriptions ........................................................................................................ 401
22.2.1
Receive Shift Register 1 (RSR1) ...................................................................... 401
22.2.2
Receive Data Register 1 (RDR1)...................................................................... 401
22.2.3
Transmit Shift Register 1 (TSR1) ..................................................................... 402
22.2.4
Transmit Data Register 1 (TDR1) .................................................................... 402
22.2.5
Serial Mode Register 1 (SMR1) ....................................................................... 403
22.2.6
Serial Control Register 1 (SCR1) ..................................................................... 406
22.2.7
Serial Status Register 1 (SSR1) ........................................................................ 410
22.2.8
Bit Rate Register 1 (BRR1) .............................................................................. 413
22.2.9
Serial Interface Mode Register 1 (SCMR1)...................................................... 420
22.2.10
Module Stop Control Register (MSTPCR)....................................................... 421
22.3 Operation .......................................................................................................................... 422
22.3.1
Overview .......................................................................................................... 422
22.3.2
Operation in Asynchronous Mode.................................................................... 424
22.3.3
Multiprocessor Communication Function ........................................................ 434
.................................................................................................. 387
.............................................. 397
Rev. 1.0, 02/00, page xi of 19
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