Hitachi H8S/2199 Hardware Manual page 5

Section 5 Exception Handling
5.1 Overview........................................................................................................................... 87
5.1.1 Exception Handling Types and Priority............................................................ 87
5.1.2 Exception Handling Operation ......................................................................... 88
5.1.3 Exception Sources and Vector Table................................................................ 88
5.2 Reset.................................................................................................................................. 90
5.2.1 Overview .......................................................................................................... 90
5.2.2 Reset Sequence ................................................................................................. 90
5.2.3 Interrupts after Reset......................................................................................... 91
5.3 Interrupts........................................................................................................................... 92
5.4 Trap Instruction................................................................................................................. 93
5.5 Stack Status after Exception Handling.............................................................................. 94
5.6 Notes on Use of the Stack ................................................................................................. 95
Section 6 Interrupt Controller
6.1 Overview........................................................................................................................... 97
6.1.1 Features............................................................................................................. 97
6.1.2 Block Diagram.................................................................................................. 98
6.1.3 Pin Configuration ............................................................................................. 99
6.1.4 Register Configuration...................................................................................... 99
6.2 Register Descriptions ........................................................................................................ 100
6.2.1 System Control Register (SYSCR)................................................................... 100
6.2.2 Interrupt Control Registers A to D (ICRA to ICRD)........................................ 101
6.2.3 IRQ Enable Register (IENR) ............................................................................ 102
6.2.4 IRQ Edge Select Registers (IEGR)................................................................... 103
6.2.5 IRQ Status Register (IRQR) ............................................................................. 104
6.2.6 Port Mode Register (PMR1) ............................................................................. 105
6.3 Interrupt Sources............................................................................................................... 106
6.3.1 External Interrupts ............................................................................................ 106
6.3.2 Internal Interrupts ............................................................................................. 107
6.3.3 Interrupt Exception Vector Table ..................................................................... 108
6.4 Interrupt Operation............................................................................................................ 111
6.4.1 Interrupt Control Modes and Interrupt Operation............................................. 111
6.4.2 Interrupt Control Mode 0.................................................................................. 113
6.4.3 Interrupt Control Mode 1.................................................................................. 115
6.4.4 Interrupt Exception Handling Sequence ........................................................... 118
6.4.5 Interrupt Response Times ................................................................................. 119
6.5 Usage Notes ...................................................................................................................... 120
6.5.1 Contention between Interrupt Generation and Disabling ................................. 120
6.5.2 Instructions that Disable Interrupts................................................................... 121
6.5.3 Interrupts during Execution of EEPMOV Instruction ...................................... 121
....................................................................................... 87
.......................................................................................... 97
Rev. 1.0, 02/00, page iii of 19