Bit Rate Register (Brr) - Hitachi H8/3032 Series Hardware Manual

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Bit 1—Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in receive data
when a multiprocessor format is used in asynchronous mode. MPB is a read-only bit and cannot
be written.
Bit 1
MPB Description
0 Multiprocessor bit value in receive data is 0*
1 Multiprocessor bit value in receive data is 1
Note: * If the RE bit is cleared to 0 when a multiprocessor format is selected, MPB retains its
previous value.
Bit 0—Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added to
transmit data when a multiprocessor format is selected for transmitting in asynchronous mode.
The MPBT setting is ignored in synchronous mode, when a multiprocessor format is not selected,
or when the SCI is not transmitting.
Bit 0
MPBT Description
0 Multiprocessor bit value in transmit data is 0
1 Multiprocessor bit value in transmit data is 1

11.2.8 Bit Rate Register (BRR)

BRR is an 8-bit register that, together with the CKS1 and CKS0 bits in SMR that select the baud
rate generator clock source, determines the serial communication bit rate.
Bit 7
Initial value 1
Read/Write R/W R/W
The CPU can always read and write BRR. BRR is initialized to H'FF by a reset and in standby
mode. The two SCI channels have independent baud rate generator control, so different values can
be set in the two channels.
Table 11-3 shows examples of BRR settings in asynchronous mode. Table 11-4 shows examples
of BRR settings in synchronous mode.
6 5 4 3
1 1 1 1
R/W R/W R/W
329
(Initial value)
(Initial value)
2 1 0
1 1 1
R/W R/W R/W