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13.3.10 Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 13.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode,
clocked synchronous mode, and Smart Card interface mode. The initial value of BRR is H'FF, and
it can be read from or written to by the CPU at all times.
Table 13.2 Relationships between The N Setting in BRR and Bit Rate B
Mode
ABCS
Asynchronous
0
mode
1
Clocked
X
synchronous
mode
Note: B: Bit rate (bps)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
ø: Operating frequency (MHz)
n and S: Determined by the SMR settings shown in the following tables.
SMR Setting
CKS1
CKS0
0
0
0
1
1
0
1
1
Table 13.3 shows sample N settings in BRR in normal asynchronous mode. Table 13.4 shows the
maximum bit rate for each frequency in normal asynchronous mode. Table 13.6 shows sample N
settings in BRR in clocked synchronous mode. Tables 13.5 and 13.7 show the maximum bit rates
with external clock input.
When the ABCS bit in SCI_0's serial extended mode register 0 (SEMR0) is set to 1 in
asynchronous mode, the maximum bit rates are twice those shown in tables 13.4 and 13.5.
Bit Rate
6
10
B =
64
2
2n-1
(N + 1)
6
10
B =
2n-1
32
2
(N + 1)
6
10
B =
8
2
2n-1
(N + 1)
Clock
Source
n
Ø
0
Ø/4
1
Ø/16
2
Ø/64
3
Error
10
Error (%) = |
2n-1
B
64
2
10
6
Error (%) = |
2n-1
B
32
2
Rev. 3.0, 10/02, page 375 of 686
6
– 1 |
100
(N + 1)
– 1 |
100
(N + 1)
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