Bit Rate Register (Brr)-H'ffd9 - Hitachi H8/329 Series Hardware Manual

8.2.8 Bit Rate Register (BRR)—H'FFD9
Bit 7
Initial value 1
Read/Write R/W
The BRR is an 8-bit register that, together with the CKS1 and CKS0 bits in the SMR, determines
the baud rate output by the baud rate generator.
The BRR is initialized to H'FF (the slowest rate) at a reset and in the standby modes.
Tables 8-3 and 8-4 show examples of BRR (N) and CKS (n) settings for commonly used bit rates.
Table 8-3. Examples of BRR Settings in Asynchronous Mode (1)
2
Bit Error
rate n N (%)
110 1 70 +0.03
150 0 207 +0.16
300 0 103 +0.16
600 0 51 +0.16
1200 0 25 +0.16
2400 0 12 +0.16
4800 — — —
9600 — — —
19200 — — —
31250 0 0 0
38400 — — —
6 5 4
1 1 1
R/W R/W R/W
XTAL frequency (MHz)
2.4576
Error
n N (%)
1 86 +0.31
0 255 0
0 127 0
0 63 0
0 31 0
0 15 0
0 7 0
0 3 0
0 1 0
— — —
0 0 0
177
3 2
1 1
R/W R/W
4
Error
n N (%)
1 141 +0.03
1 103 +0.16
0 207 +0.16
0 103 +0.16
0 51 +0.16
0 25 +0.16
0 12 +0.16
— — —
— — —
0 1 0
— — —
1 0
1 1
R/W R/W
4.194304
Error
n N (%)
1 148 –0.04
1 108 +0.21
0 217 +0.21
0 108 +0.21
0 54 –0.70
0 26 +1.14
0 13 –2.48
0 6 –2.48
— — —
— — —
— — —