13.2.8
Bit Rate Register (BRR)
The bit rate register (BRR) is an eight-bit register that, together with the baud rate generator clock
source selected by the CKS1 and CKS0 bits in the serial mode register (SMR), determines the
serial transmit/receive bit rate.
The CPU can always read and write the BRR. The BRR is initialized to H'FF by a reset or in
standby mode.
Bit:
Bit name:
Initial value:
R/W:
Table 13.3 shows examples of BRR settings in the asynchronous mode; table 13.4 shows
examples of BBR settings in the clocked synchronous mode.
336 Hitachi
7
6
1
1
R/W
R/W
R/W
5
4
3
1
1
1
R/W
R/W
2
1
1
1
R/W
R/W
R/W
0
1