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14.2.9
Bit Rate Register (SCBRR)
The bit rate register (SCBRR) is an 8-bit register that, together with the baud rate generator clock
source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the
serial transmit/receive bit rate.
The CPU can always read and write to SCBRR. SCBRR is initialized to H'FF by a reset, and in
module standby or standby mode. Each channel has independent baud rate generator control, so
different values can be set in two channels.
Bit:
Initial value:
R/W:
R/W
The SCBRR setting is calculated as follows:
Asynchronous mode: N =
Synchronous mode: N =
B:
Bit rate (bits/s)
SCBRR setting for baud rate generator (0 ≤ N ≤ 255)
N:
Pφ: Operating frequency for peripheral modules (MHz)
Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of
n:
n, see table 14.3.)
Table 14.3 SCSMR Settings
n
0
1
2
3
Note: The bit rate error in asynchronous is given by the following formula:
Error (%) = (
(N + 1) × B × 64 × 2
7
6
5
1
1
1
R/W
R/W
Pφ
64 × 2
2n – 1
Pφ
8 × 2
2n – 1
Clock Source
Pφ
Pφ/4
Pφ/16
Pφ/64
Pφ × 10
6
2n – 1
4
3
1
1
R/W
R/W
R/W
× 10
6
– 1
× B
× 10
6
– 1
× B
SCSMR Settings
CKS1
0
0
1
1
) × 100
2
1
0
1
1
1
R/W
R/W
CKS0
0
1
0
1
451
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