Bit Rate Register (Brr) - Hitachi H8/3006 Hardware Manual

Bit 1—Multiprocessor bit (MPB): Stores the value of the multiprocessor bit in the receive data
when a multiprocessor format is used in asynchronous mode. MPB is a read-only bit, and cannot
be written.
Bit 1
MPB Description
0 Multiprocessor bit value in receive data is 0*
1 Multiprocessor bit value in receive data is 1
Note: * If the RE bit in SCR is cleared to 0 when a multiprocessor format is selected, MPB
retains its previous value.
Bit 0—Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added to
transmit data when a multiprocessor format in selected for transmitting in asynchronous mode.
The MPBT bit setting is ignored in synchronous mode, when a multiprocessor format is not
selected, or when the SCI cannot transmit.
Bit 0
MPBT Description
0 Multiprocessor bit value in transmit data is 0
1 Multiprocessor bit value in transmit data is 1
13.2.8

Bit Rate Register (BRR)

BRR is an 8-bit register that, together with the CKS1 and CKS0 bits in SMR that select the baud
rate generator clock source, determines the serial communication bit rate.
7
Bit
1
Initial value
Read/Write
R/W
The CPU can always read and write BRR. BRR is initialized to H'FF by a reset and in standby
mode. Each SCI channel has independent baud rate generator control, so different values can be
set in the three channels.
Table 13.3 shows examples of BRR settings in asynchronous mode. Table 13.4 shows examples
of BRR settings in synchronous mode.
446
6 5
1 1
R/W R/W
4 3
1
1
R/W
R/W
(Initial value)
(Initial value)
2 1
1 1
R/W R/W
0
1
R/W