Execution Synchronization; Instruction-Related Exceptions; Instruction Set Overview - Freescale Semiconductor MPC850 User Manual

5.2.2.3.2 Execution Synchronization

An instruction is execution synchronizing if all previously initiated instructions appear to
have completed before the instruction is initiated or, in the case of the Synchronize (sync)
and Instruction Synchronize (isync) instructions, before the instruction completes. For
example, the Move to Machine State Register (mtmsr) instruction is execution
synchronizing. It ensures that all preceding instructions have completed execution and will
not cause an exception before the instruction executes, but does not ensure subsequent
instructions execute in the newly established environment. For example, if the mtmsr sets
the MSR[PR] bit, unless an isync immediately follows the mtmsr instruction, a privileged
instruction could be executed or privileged access could be performed without causing an
exception even though the MSR[PR] bit indicates user mode.

5.2.2.3.3 Instruction-Related Exceptions

There are two kinds of exceptions in the MPC850—those caused directly by the execution
of an instruction and those caused by an asynchronous event. Either may cause components
of the system software to be invoked.
Exceptions can be caused directly by the execution of an instruction as follows:
• An attempt to execute an illegal instruction causes the illegal instruction (program
exception) handler to be invoked. An attempt by a user-level program to execute the
supervisor-level instructions listed below causes the privileged instruction (program
exception) handler to be invoked. The MPC850 provides the following
supervisor-level instructions—dcbi, mfmsr, mfspr, mtmsr, mtspr, rfi, tlbie, and
tlbsync. Note that the privilege level of the mfspr and mtspr instructions depends
on the SPR encoding.
• An attempt to access memory that is not available (page fault) causes the ISI
exception handler to be invoked.
• An attempt to access memory with an effective address alignment that is invalid for
the instruction causes the alignment exception handler to be invoked. See
Section 6.1.2.6, "Alignment Exception (0x00600)," for restrictions on operand
alignment.
• The execution of an sc instruction invokes the system call exception handler that
permits a program to request the system to perform a service.
• The execution of a trap instruction invokes the program exception trap handler.
Exceptions caused by asynchronous events are described in Chapter 6, "Exceptions."

5.2.3 Instruction Set Overview

This section provides a brief overview of the PowerPC instructions implemented in the
MPC850 and highlights any special information with respect to how the MPC850
implements a particular instruction. Note that the categories used in this section correspond
to those used in Chapter 4, "Addressing Modes and Instruction Set Summary," in The
Chapter 5. MPC850 Instruction Set
Instruction Set Summary