Architecture - Freescale Semiconductor PowerPC MPC823 Reference Manual

Introduction
• Development Capabilities and Interface
Program Flow Tracking
— Instruction Show Cycle
— Data Show Cycle
— Branching
— Exception Traps
Watchpoints and Breakpoints
— Four Hardware Breakpoints
— Five Watchpoint Sources
Simple Hardware Interface
— High-Speed Data Transfer
— Internal Status Pins
— Freeze Indication
Rich Control Register Set
• IEEE 1149.1 Test Access Port (JTAG)
• 3.3V Operation with 5V TTL Compatibility for the JTAG and Communication Processor
Module Port Pins and 3.3V for All Others.
• 256-Pin Plastic Ball Grid Array (BGA) Packaging

1.2 ARCHITECTURE

The MPC823 microprocessor uses a dual-processor architecture design approach to
provide high performance using a general-purpose RISC integer processor and a special-
purpose 32-bit scalar RISC communication processor module. The peripherals are uniquely
designed for communication requirements and can provide embedded signal processing
functions for communication and user interface enhancements and the I/O support needed
for high-speed digital communications. The MPC823 is comprised of four main modules that
interface with the 32-bit internal bus:
• The embedded PowerPC core
• The system interface unit
• The communication processor module
• LCD controller
The MPC823 block diagram is illustrated in Figure 1-1.
MPC823 REFERENCE MANUAL