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•
Supervisor level—This defines supervisor-level resources typically required by an operating
system, the memory management model, supervisor-level registers, and the exception model.
In general, the e200z3 core supports the user-level architecture from the original PowerPC architecture.
The following sections are intended to highlight the main differences. For specific implementation details
refer to the relevant chapter.
1.7.1
Instruction Set Compatibility
The following sections describe the user and supervisor instruction sets.
1.7.1.1
User Instruction Set
The e200z3 core family executes legacy user-mode binaries and object files except for the following:
•
The e200z3 core supports vector and scalar single-precision floating-point operations. These
instructions have different encoding than the original definition of the PowerPC architecture.
Additionally, the e200z3 core uses GPRs for floating-point operations, rather than the FPRs
defined by the UISA. Most porting of floating-point operations can be handled by recompiling.
•
String instructions are not implemented on the e200z3 core; therefore, trap emulation must be
provided to ensure backward compatibility.
1.7.1.2
Supervisor Instruction Set
The supervisor-mode instruction set in the original PowerPC architecture is compatible with the e200z3
core with the following exceptions:
•
The MMU architecture is different, so some TLB manipulation instructions have different
semantics.
•
Instructions that support BATs and segment registers are not implemented.
1.7.2
Memory Subsystem
Both the Power ISA and the original version of the PowerPC architecture provide separate instruction and
data memory resources. The e200z3 core provides optional additional cache control features, including
cache locking. Note that the core implementations described in this document do not implement caches.
1.7.3
Interrupt Handling
Exception handling is generally the same as that defined in the original version of the PowerPC
architecture for the e200z3 core, with the following differences:
•
The Power ISA defines a new critical interrupt, providing an interrupt nesting. The critical interrupt
includes critical input and watchdog timer time-out inputs.
•
The debug interrupt, originally implementation-specific, is now included in the Power ISA. It
defines the Return from Debug Interrupt instruction, rfdi, and two debug save/restore registers,
DSRR0 and DSRR1.
Freescale Semiconductor
e200z3 Power Architecture Core Reference Manual, Rev. 2
e200z335 Core Complex Overview
1-15
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