Acmp Control And Status Register (Acmp_Cs) - Freescale Semiconductor MC9S08PT60 Reference Manual

Memory map and register definition

20.3.1 ACMP Control and Status Register (ACMP_CS)

Address: 2Ch base + 0h offset = 2Ch
Bit 7
Read
ACE
Write
Reset 0
Field
7 Analog Comparator Enable
ACE
Enables the ACMP module.
0 The ACMP is disabled.
1 The ACMP is enabled.
6 Analog Comparator Hysterisis Selection
HYST
Selects ACMP hysterisis.
0 20 mV.
1 30 mV.
5 ACMP Interrupt Flag Bit
ACF
Synchronously set by hardware when ACMP output has a valid edge defined by ACMOD. The setting of
this bit lags the ACMPO to bus clocks. Clear ACF bit by writing a 0 to this bit. Writing a 1 to this bit has no
effect.
4 ACMP Interrupt Enable
ACIE
Enables an ACMP CPU interrupt.
0 Disable the ACMP Interrupt.
1 Enable the ACMP Interrupt.
3 ACMP Output
ACO
Reading ACO will return the current value of the analog comparator output. ACO is reset to a 0 and will
read as a 0 when the ACMP is disabled (ACE = 0)
2 ACMP Output Pin Enable
ACOPE
ACOPE enables the pad logic so that the output can be placed onto an external pin.
0 ACMP output cannot be placed onto external pin.
1 ACMP output can be placed onto external pin.
ACMOD ACMP MOD
Determines the sensitivity modes of the interrupt trigger.
00 ACMP interrupt on output falling edge.
01 ACMP interrupt on output rising edge.
574
6 5
HYST ACF ACIE
0 0
ACMP_CS field descriptions
Table continues on the next page...
MC9S08PT60 Reference Manual, Rev. 4, 08/2014
4 3 2
ACO
ACOPE
0 0 0
Description
1 0
ACMOD
0 0
Freescale Semiconductor, Inc.