Pci Type 0 Configuration Registers - Freescale Semiconductor MCF5480 Reference Manual

Address
MBAR + 0x8480
MBAR + 0x8484
MBAR + 0x8488
MBAR + 0x848C
MBAR + 0x8490
MBAR + 0x8494
MBAR + 0x8498
MBAR + 0x849C
MBAR + 0x84A0–0x84BC
MBAR + 0x84C0
MBAR + 0x84C4
MBAR + 0x84C8
MBAR + 0x84CC
MBAR + 0x84D0
MBAR + 0x84D4
MBAR + 0x84D8–0x84FC
1
The PCI controller has separate control registers for transmit and receive operations via the communication subsystem
DMA. See Section 19.3.3, "Communication Subsystem Interface
19.3.1

PCI Type 0 Configuration Registers

The PCI controller supplies a type 0 PCI configuration space header. These registers are accessible as an
offset from MBAR or through externally mastered PCI configuration cycles. PCI Dword Reserved space
(0x10–0x3F) can be accessed only from external PCI configuration accesses.
19-6
Table 19-2. PCI Memory Map (Continued)
Name Size
CommBus FIFO Receive Interface Registers
PCIRPSR 32
PCIRSAR 32
PCIRTCR 32
PCIRER 32
PCIRNAR 32
— —
PCIRDCR 32
PCIRSR 32
— —
PCIRFDR 32
PCIRFSR 32
PCIRFCR 32
PCIRFAR 32
PCIRFRPR 32
PCIRFWPR 32
— —
MCF548x Reference Manual, Rev. 3
Description
1
Rx Packet Size Register
Rx Start Address Register
Rx Transaction Control Register
Rx Enables Register
Rx Next Address Register
Reserved
Rx Done Counts Register
Rx Status Register
Reserved
Rx FIFO Data Register
Rx FIFO Status Register
Rx FIFO Control Register
Rx FIFO Alarm Register
Rx FIFO Read Pointer Register
Rx FIFO Write Pointer Register
Reserved
Registers" for more information on these registers.
Access
R/W
R/W
R/W
R/W
R
—
R
R/WC
—
R/W
R/WC
R/W
R/W
R/W
R/W
—
Freescale Semiconductor