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3.3 Reset and Configuration Signals
Signal Name
PORESET
HRESET
SRESET
M3_RESET
STOP_BS
RC_LDF
GPIO14
IRQ8
URXD
Freescale Semiconductor
Table 3-5. Reset and Configuration Signals
Type
Input
Power-On Reset
When asserted, this line causes the MSC8144E to enter power-on reset state.
Internally, this signal also resets the TAP and debugging modules. The power-on
reset flow resets the MSC8144E device, configures various device attributes
including its clock modes, and drives HRESET and SRESET as open-drain outputs.
Input/
Hard Reset
Output
When asserted as an input, this signal causes the MSC8144E to abort all current
internal and external transactions, set most registers to their default state, and enter
the hard reset state. This signal must be asserted for at least 32 CLKIN cycles.
While the device is in the hard reset state, it drives HRESET and SRESET as
open-drain outputs. This signal requires an external pull-up resistor. The signal is
tri-stated after the hard reset flow is complete.
Input/
Soft Reset
Output
When asserted as an input, this signal causes the MSC8144E to enter the soft reset
state, about all current internal transactions, configure most registers with their
default values, and cause the cores to enter their reset state. The signal does not
affect I/O signal functionality or direction or memory controller operations. While the
device is in the soft reset state, it drives the SRESET as an open-drain output. This
signal requires an external pull-up resistor. The signal is tri-stated after the soft reset
flow is complete.
Input
M3 Memory Reset
When asserted, this line causes the M3 memory to enter the reset state.
When using the M3 memory, connect to 2.5 V using the same logic as PORESET.
Input
Stop Boot Sequencer
This signal is valid only when the reset configuration words are being loaded from
2
an I
C EEPROM using the boot sequencer and is asserted only for a reset target
device to prevent the loading of the reset configuration words until allowed by the
Boot ROM. The signal level must be asserted as long as HRESET is asserted. For
the reset master or a single device reading from I
low during the reset sequence. For details, see Chapter 5, Reset. This signal is also
used for booting after reset (for details, see Chapter 6, Boot Program).
Output
Reset Configuration Word Load Failure
Used by the core to signal when the reset configuration word fails to load from an
2
I
C EEPROM when using the boot sequencer. It indicates whether the boot
sequencer failed, which can be due to an incorrect data structure or an I
failure. The signal can be asserted anytime during HRESET assertion. Once
asserted, the device holds HRESET low until the PORESET is restarted.
Input/
General-Purpose Input Output 14
Output
One of 32 GPIO pins used as GPIO or as a dedicated input or output. For details,
see Chapter 23, GPIO.
Input
Interrupt Request 8
One of the sixteen external lines that can request a service routine, via the internal
interrupt controller, from the SC3400 cores.
Input/
UART Receive Data
Output
For details, see Chapter 21, UART.
MSC8144E Reference Manual, Rev. 3
Reset and Configuration Signals
Signal Description
2
C EEPROM, you must drive this
2
C bus
3-7
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