Download  Print this page

Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 1 01-2011 Datasheet

2nd generation core processor family desktop
Hide thumbs

Advertisement

Quick Links

®
2nd Generation Intel
Core™
Processor Family Desktop
Datasheet, Volume 1
®
Supporting Intel
Core™ i7, i5 and i3 Desktop Processor Series
This is Volume 1 of 2
January 2011
Document Number: 324641-001

Advertisement

loading

  Also See for Intel 2ND GENERATION INTEL CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 1 01-2011

  Related Manuals for Intel 2ND GENERATION INTEL CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 1 01-2011

  Summary of Contents for Intel 2ND GENERATION INTEL CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 1 01-2011

  • Page 1 ® 2nd Generation Intel Core™ Processor Family Desktop Datasheet, Volume 1 ® Supporting Intel Core™ i7, i5 and i3 Desktop Processor Series This is Volume 1 of 2 January 2011 Document Number: 324641-001...
  • Page 2 Code Modules and an Intel TXT-compatible measured launched environment (MLE). The MLE could consist of a virtual machine monitor, an OS or an application. In addition, Intel TXT requires the system to contain a TPM v1.2, as defined by the Trusted Computing Group and specific software for some uses.
  • Page 3: Table Of Contents

    1.2.4 Platform Environment Control Interface (PECI) ........... 14 1.2.5 Processor Graphics ................. 14 ® ® 1.2.6 Intel Flexible Display Interface (Intel FDI) ..........14 Power Management Support ................15 1.3.1 Processor Core..................15 1.3.2 System ....................15 1.3.3 Memory Controller.................. 15 1.3.4...
  • Page 4 Processor Graphics Display ..............31 2.4.2.1 Display Planes ................31 2.4.2.2 Display Pipes ................32 2.4.2.3 Display Ports ................32 2.4.3 Intel Flexible Display Interface..............32 2.4.4 Multi-Graphics Controller Multi-Monitor Support ..........32 Platform Environment Control Interface (PECI) ............33 Interface Clocking....................33 2.6.1 Internal Clocking Requirements ..............33 Technologies......................35 ®...
  • Page 5 PCIe* Power Management .................. 54 DMI Power Management..................55 Graphics Power Management ................55 4.6.1 Intel® Rapid Memory Power Management (RMPM) (also know as CxSR) ..55 4.6.2 Intel® Graphics Performance Modulation Technology(GPMT) ......55 4.6.3 Graphics Render C-State ................. 55 ®...
  • Page 6 Figures ® 2nd Generation Intel Core™ Processor Family Desktop Platform ........10 ® Intel Flex Memory Technology Operation ..............21 PCI Express* Layering Diagram.................24 Packet Flow through the Layers.................25 PCI Express* Related Register Structures in the Processor ..........26 PCIe Typical Operation 16 lanes Mapping..............27 Processor Graphics Controller Unit Block Diagram ............28...
  • Page 7 Memory Reference and Compensation ............... 61 Reset and Miscellaneous Signals ................62 PCI Express* Graphics Interface Signals ..............63 ® Intel Flexible Display Interface ................63 DMI - Processor to PCH Serial Interface ..............64 PLL Signals ......................64 6-10 TAP Signals......................64 6-11 Error and Thermal Protection..................
  • Page 8: Revision History

    Revision History Revision Revision Description Number Date January Initial release 2011 § § Datasheet, Volume 1...
  • Page 9: Introduction

    Throughout this document, the Intel 6 Series Chipset Platform Controller Hub may also be referred to as “PCH”. ® Note: Throughout this document, 2nd Generation Intel Core™ processor family desktop may be referred to as simply the processor. ® Note: Throughout this document, the Intel Core™...
  • Page 10: 2Nd Generation Intel ® Core™ Processor Family Desktop Platform

    Introduction ® Figure 1-1. 2nd Generation Intel Core™ Processor Family Desktop Platform PC I Express* 2.0 DDR3 1 x16 or 2x8 Discrete Graphics (PEG) Processor PECI DMI2 x4 Serial ATA Intel® Management Digital Display x 3 Engine USB 2.0 Platform...
  • Page 11: Processor Feature Details

    • A 256-KB shared instruction/data second-level cache (L2) for each core • Up to 8-MB shared instruction/data third-level cache (L3), shared among all cores 1.1.1 Supported Technologies ® ® • Intel Virtualization Technology for Directed I/O (Intel VT-d) ® ® • Intel Virtualization Technology (Intel VT-x) ®...
  • Page 12: Pci Express

    • Command launch modes of 1n/2n • On-Die Termination (ODT) • Asynchronous ODT ® ® • Intel Fast Memory Access (Intel FMA) — Just-in-Time Command Scheduling — Command Overlap — Out-of-Order Scheduling 1.2.2 PCI Express* • The PCI Express* port(s) are fully-compliant to the PCI Express Base Specification, Revision 2.0.
  • Page 13: Direct Media Interface (Dmi)

    Introduction • Traditional AGP style traffic (asynchronous non-snooped, PCI-X Relaxed ordering) • Peer segment destination posted write traffic (no peer-to-peer read traffic) in Virtual Channel 0 — DMI -> PCI Express* Port 0 • 64-bit downstream address format, but the processor never generates an address above 64 GB (Bits 63:36 will always be zeros) •...
  • Page 14: Platform Environment Control Interface (Peci)

    • The Processor Graphics contains a refresh of the sixth generation graphics core enabling substantial gains in performance and lower power consumption. • Next Generation Intel Clear Video Technology HD support is a collection of video playback and enhancement features that improve the end user’s viewing experience.
  • Page 15: Power Management Support

    • L0s and L1 ASPM power management capability 1.3.6 Processor Graphics Controller • Rapid Memory Power Management RMPM – CxSR • Graphics Performance Modulation Technology (GPMT) • Intel Smart 2D Display Technology (Intel S2DDT) • Graphics Render C-State (RC6) Thermal Management Support • Digital Thermal Sensor ®...
  • Page 16: Package

    • The processor socket type is noted as LGA 1155. The package is a 37.5 x 37.5 mm ® Flip Chip Land Grid Array (FCLGA 1155). See the 2nd Generation Intel Core™ Processor and LGA1155 Socket Thermal Mechanical Specifications and Design Guidelines for complete details on package.
  • Page 17 Each execution core has an instruction cache, data cache, and 256-KB L2 cache. All execution cores share the L3 cache. ® Processor Graphics Intel Processor Graphics A unit of DRAM corresponding four to eight devices in parallel, ignoring ECC. Rank These devices are usually, but not always, mounted on a single side of a SO- DIMM.
  • Page 18: Related Documents

    Related Documents Refer to Table 1-2 for additional information. Table 1-2. Related Documents Document Document Number/ Location ® 2nd Generation Intel Core™ Processor Family Desktop Datasheet, http://download.intel.com/design /processor/datashts/324642.pdf Volume 2 ® 2nd Generation Intel Core™ Processor Family Desktop Specification http://download.intel.com/design /processor/specupdt/324643.pdf...
  • Page 19: Interfaces

    Interfaces Interfaces This chapter describes the interfaces supported by the processor. System Memory Interface 2.1.1 System Memory Technology Supported The Integrated Memory Controller (IMC) supports DDR3 protocols with two independent, 64-bit wide channels each accessing one or two DIMMs. The type of memory supported by the processor is dependant on the PCH SKU in the target platform.
  • Page 20: System Memory Timing Support

    Interfaces Table 2-2. Supported SO-DIMM Module Configurations (AIO Only) # of # of # of # of Banks DIMM DRAM Device DRAM Physical Card DRAM Row/Col Inside Page Size Capacity Technology Organization Device Version Devices Address Bits DRAM Ranks 1 GB 1 Gb 64 M x 16 13/10...
  • Page 21: System Memory Organization Modes

    Dual-Channel Mode – Intel Flex Memory Technology Mode The IMC supports Intel Flex Memory Technology Mode. Memory is divided into a symmetric and an asymmetric zone. The symmetric zone starts at the lowest address in each channel and is contiguous until the asymmetric zone begins or until the top address of the channel with the smaller capacity is reached.
  • Page 22: Rules For Populating Memory Slots

    ® (Intel FMA) The following sections describe the Just-in-Time Scheduling, Command Overlap, and Out-of-Order Scheduling Intel FMA technology enhancements. 2.1.5.1 Just-in-Time Command Scheduling The memory controller has an advanced command scheduler where all pending requests are examined simultaneously to determine the most efficient request to be issued next.
  • Page 23: Command Overlap

    Interfaces 2.1.5.2 Command Overlap Command Overlap allows the insertion of the DRAM commands between the Activate, Precharge, and Read/Write commands normally used, as long as the inserted commands do not affect the currently executing command. Multiple commands can be issued in an overlapping manner, increasing the efficiency of system memory protocol. 2.1.5.3 Out-of-Order Scheduling While leveraging the Just-in-Time Scheduling and Command Overlap enhancements,...
  • Page 24: Pci Express* Interface

    Interfaces PCI Express* Interface This section describes the PCI Express interface capabilities of the processor. See the PCI Express Base Specification for details of PCI Express. The number of PCI Express controllers is dependent on the platform. Refer to Chapter 1 for details.
  • Page 25: Transaction Layer

    Interfaces packets get transformed from their Physical Layer representation to the Data Link Layer representation and finally (for Transaction Layer Packets) to the form that can be processed by the Transaction Layer of the receiving device. Figure 2-3. Packet Flow through the Layers 2.2.1.1 Transaction Layer The upper layer of the PCI Express architecture is the Transaction Layer.
  • Page 26: Pci Express* Configuration Mechanism

    Interfaces 2.2.2 PCI Express* Configuration Mechanism The PCI Express (external graphics) link is mapped through a PCI-to-PCI bridge structure. Figure 2-4. PCI Express* Related Register Structures in the Processor PCI-PCI Bridge representing Compatible PEG0 Express root PCI Host Bridge Device Express ports Device (Device 1 and...
  • Page 27: Pci Express Lanes Connection

    GPE. Any DMI related SERR activity is associated with Device 0. 2.3.2 Processor/PCH Compatibility Assumptions ® The processor is compatible with the PCH. The processor is not Intel 6 Series Chipset compatible with any previous PCH products. Datasheet, Volume 1...
  • Page 28: Dmi Link Down

    Interfaces 2.3.3 DMI Link Down The DMI link going down is a fatal, unrecoverable error. If the DMI data link goes to data link down, after the link was up, then the DMI link hangs the system by not allowing the link to retrain to prevent data corruption. This link behavior is controlled by the PCH.
  • Page 29: And Video Engines For Graphics Processing

    Interfaces 2.4.1 3D and Video Engines for Graphics Processing The 3D graphics pipeline architecture simultaneously operates on different primitives or on different portions of the same primitive. All the cores are fully programmable, increasing the versatility of the 3D Engine. The Gen 6.0 3D engine provides the following performance and power-management enhancements: •...
  • Page 30: Video Engine

    Interfaces 2.4.1.2.6 Windower/IZ (WIZ) Stage The WIZ unit performs an early depth test, which removes failing pixels and eliminates unnecessary processing overhead. The Windower uses the parameters provided by the SF unit in the object-specific rasterization algorithms. The WIZ unit rasterizes objects into the corresponding set of pixels.
  • Page 31: Processor Graphics Display

    2.4.2 Processor Graphics Display The Processor Graphics controller display pipe can be broken down into three components: • Display Planes • Display Pipes ® • DisplayPort and Intel Figure 2-7. Processor Display Block Diagram Display Display Port Pipe A Control...
  • Page 32: Display Pipes

    FDI) is a proprietary link for carrying display ® traffic from the Processor Graphics controller to the PCH display I/Os. Intel supports two independent channels—one for pipe A and one for pipe B. • Each channel has four transmit (Tx) differential pairs used for transporting pixel and framing data from the display engine.
  • Page 33: Platform Environment Control Interface (Peci)

    Interfaces Platform Environment Control Interface (PECI) The PECI is a one-wire interface that provides a communication channel between a PECI client (processor) and a PECI master. The processor implements a PECI interface • Allow communication of processor thermal and other information to the PECI master.
  • Page 34 Interfaces Datasheet, Volume 1...
  • Page 35: Technologies

    OSs and applications without any special steps. • Enhanced: Intel VT enables VMMs to run 64-bit guest operating systems on IA x86 processors. • More reliable: Due to the hardware support, VMMs can now be smaller, less complex, and more efficient.
  • Page 36: Intel Vt-X Features

    3.1.3 Intel VT-d Objectives The key Intel VT-d objectives are domain-based isolation and hardware-based virtualization. A domain can be abstractly defined as an isolated environment in a platform to which a subset of host physical memory is allocated. Virtualization allows for the creation of one or more partitions on a single system.
  • Page 37: Intel Vt-D Features

    The following features are not supported by the processor with Intel VT-d: • No support for PCISIG endpoint caching (ATS) • No support for Intel VT-d read prefetching/snarfing (that is, translations within a cacheline are not stored in an internal buffer for reuse for subsequent translations).
  • Page 38: Intel Trusted Execution Technology (Intel Txt)

    Intel TXT is a set of extensions designed to provide a measured and controlled launch of system software that will then establish a protected environment for itself and any additional software that it may execute.
  • Page 39: Intel Turbo Boost Technology

    Turbo Boost Technology is a feature that allows the processor core to opportunistically and automatically run faster than its rated operating frequency/render clock if it is operating below power, temperature, and current limits. The Intel Turbo Boost Technology feature is designed to increase performance of both multi-threaded and single-threaded workloads.
  • Page 40: Intel Advanced Vector Extensions (Avx)

    Intel Advanced Vector Extensions (AVX) ® Intel Advanced Vector Extensions (AVX) is the latest expansion of the Intel instruction ® set. It extends the Intel Streaming SIMD Extensions (SSE) from 128-bit vectors into 256-bit vectors. Intel AVX addresses the continued need for vector floating-point...
  • Page 41: Intel ® 64 Architecture X2Apic

    Technologies ® Intel 64 Architecture x2APIC The x2APIC architecture extends the xAPIC architecture that provides a key mechanism for interrupt delivery. This extension is intended primarily to increase processor addressability. Specifically, x2APIC: • Retains all key elements of compatibility to the xAPIC architecture —...
  • Page 42 The x2APIC architecture provides backward compatibility to the xAPIC architecture and forward extendibility for future Intel platform innovations. Note: Intel x2APIC technology may not be available on all processor SKUs. ® For more information, refer to the Intel 64 Architecture x2APIC Specification at http://www.intel.com/products/processor/manuals/...
  • Page 43: Power Management

    Power Management Power Management This chapter provides information on the following power management topics: • ACPI States • Processor Core • Integrated Memory Controller (IMC) • PCI Express* • Direct Media Interface (DMI) • Processor Graphics Controller ACPI States Supported The ACPI states supported by the processor are described in this section.
  • Page 44: Integrated Memory Controller States

    Power Management 4.1.3 Integrated Memory Controller States Table 4-3. Integrated Memory Controller States State Description Power up CKE asserted. Active mode. Pre-charge CKE de-asserted (not self-refresh) with all banks closed. Power-down Active Power- CKE de-asserted (not self-refresh) with minimum one bank active. Down Self-Refresh CKE de-asserted using device self-refresh.
  • Page 45: Interface State Combinations

    Enhanced Intel SpeedStep Technology The following are the key features of Enhanced Intel SpeedStep Technology: • Multiple frequency and voltage points for optimal performance and power efficiency. These operating points are known as P-states. • Frequency selection is software controlled by writing to processor MSRs. The voltage is optimized based on the selected frequency and the number of active processor cores.
  • Page 46: Low-Power Idle States

    C-states have longer exit and entry latencies. Resolution of C-states occur at the thread, processor core, and processor package level. Thread-level C-states are available if Intel Hyper-Threading Technology is enabled. Caution: Long term reliability cannot be assured unless all the Low Power Idle States are enabled.
  • Page 47: Requesting Low-Power Idle States

    Power Management Table 4-8. Coordination of Thread Power States at the Core Level Thread 1 Processor Core C-State Thread 0 Note: If enabled, the core C-state will be C1E if all enabled cores have also resolved a core C1 state or higher. 4.2.3 Requesting Low-Power Idle States The primary software interfaces for requesting low power idle states are through the...
  • Page 48: Core C-States

    MWAIT(C1/C1E) instruction. A System Management Interrupt (SMI) handler returns execution to either Normal ® state or the C1/C1E state. See the Intel 64 and IA-32 Architecture Software Developer’s Manual, Volume 3A/3B: System Programmer’s Guide for more information. While a core is in C1/C1E state, it processes bus snoops and snoops from other threads.
  • Page 49: Package C-States

    Power Management There are two C-State auto-demotion options: • C6 to C3 • C6/C3 To C1 The decision to demote a core from C6 to C3 or C3/C6 to C1 is based on each core’s immediate residency history. Upon each core C6 request, the core C-state is demoted to C3 or C1 until a sufficient amount of residency has been established.
  • Page 50: Package C0

    Power Management Table 4-10. Coordination of Core Power States at the Package Level Core 1 Package C-State Core 0 Note: If enabled, the package C-state will be C1E if all cores have resolved a core C1 state or higher. Figure 4-3. Package C-State Entry and Exit 4.2.5.1 Package C0...
  • Page 51: Package C1/C1E

    Power Management 4.2.5.2 Package C1/C1E No additional power reduction actions are taken in the package C1 state. However, if the C1E sub-state is enabled, the processor automatically transitions to the lowest supported core clock frequency, followed by a reduction in voltage. The package enters the C1 low power state when: •...
  • Page 52: Imc Power Management

    Power Management IMC Power Management The main memory is power managed during normal operation and in low-power ACPI Cx states. 4.3.1 Disabling Unused System Memory Outputs Any system memory (SM) interface signal that goes to a memory module connector in which it is not connected to any actual memory devices (such as DIMM connector is unpopulated, or is single-sided) is tri-stated.
  • Page 53 Power Management The processor supports 5 different types of power-down. The different modes are the power-down modes supported by DDR3 and combinations of these. The type of CKE power-down is defined by the configuration. The are options are: 1. No power-down 2.
  • Page 54: Initialization Role Of Cke

    4.3.2.2 Conditional Self-Refresh Intel Rapid Memory Power Management (Intel RMPM) conditionally places memory into self-refresh in the package C3 and C6 low-power states. RMPM functionality depends on the graphics/display state (relevant only when processor graphics is being used), as well as memory traffic patterns generated by other connected I/O devices.
  • Page 55: Dmi Power Management

    Technology(GPMT) ® Intel Graphics Power Modulation Technology (Intel GPMT) is a method for saving power in the graphics adapter while continuing to display and process data in the adapter. This method will switch the render frequency and/or render voltage dynamically between higher and lower power states supported on the platform based on render engine workload.
  • Page 56: Thermal Power Management

    Graphics Dynamic Frequency Technology is the ability of the processor and graphics cores to opportunistically increase frequency and/or voltage above the ® ensured processor and graphics frequency for the given part. Intel Graphics Dynamic Frequency Technology is a performance feature that makes use of unused package power and thermals to increase application performance.
  • Page 57: Thermal Management

    Thermal Management Thermal Management ® For thermal specifications and design guidelines, refer to the 2nd Generation Intel Core™ Processor Family Desktop and LGA1155 Socket Thermal and Mechanical Specifications and Design Guidelines. § § Datasheet, Volume 1...
  • Page 58 Thermal Management Datasheet, Volume 1...
  • Page 59: Signal Description

    Signal Description Signal Description This chapter describes the processor signals. They are arranged in functional groups according to their associated interface or category. The following notations are used to describe the signal type. Notations Signal Type Input Pin Output Pin Bi-directional Input/Output Pin The signal description also includes the type of buffer used for the particular signal (see Table...
  • Page 60: System Memory Interface

    Signal Description System Memory Interface Table 6-2. Memory Channel A Direction/ Signal Name Description Buffer Type Bank Select: These signals define which banks are selected within SA_BS[2:0] each SDRAM rank. DDR3 Write Enable Control Signal: This signal is used with SA_RAS# and SA_WE# SA_CAS# (along with SA_CS#) to define the SDRAM Commands.
  • Page 61: Memory Reference And Compensation

    Signal Description Table 6-3. Memory Channel B Direction/ Signal Name Description Buffer Type Bank Select: These signals define which banks are selected within SB_BS[2:0] each SDRAM rank. DDR3 Write Enable Control Signal: This signal is used with SB_RAS# and SB_WE# SB_CAS# (along with SB_CS#) to define the SDRAM Commands.
  • Page 62: Reset And Miscellaneous Signals

    Signal Description Reset and Miscellaneous Signals Table 6-5. Reset and Miscellaneous Signals Direction/ Signal Name Description Buffer Type Configuration Signals: The CFG signals have a default value of '1' if not terminated on the board. • CFG[1:0]: Reserved configuration lane. A test point may be placed on the board for this lane.
  • Page 63: Pci Express* Based Interface Signals

    PCI Express Transmit Differential Pair PEG_TX#[15:0] PE_TX[3:0] PCI Express PE_TX#[3:0] Notes: PE_TX[3:0] and PE_RX[3:0] are only used for platforms that support 20 PCIe lanes. ® Intel Flexible Display Interface Signals ® Table 6-7. Intel Flexible Display Interface Direction/ Signal Name...
  • Page 64: Dmi

    Signal Description Table 6-8. DMI - Processor to PCH Serial Interface Direction/ Signal Name Description Buffer Type DMI_RX[3:0] DMI Input from PCH: Direct Media Interface receive differential pair. DMI_RX#[3:0] DMI_TX[3:0] DMI Output to PCH: Direct Media Interface transmit differential pair. DMI_TX#[3:0] PLL Signals Table 6-9.
  • Page 65: Error And Thermal Protection

    Signal Description Error and Thermal Protection Table 6-11. Error and Thermal Protection Direction/ Signal Name Description Buffer Type Catastrophic Error: This signal indicates that the system has experienced a catastrophic error and cannot continue to operate. The processor will set this for non-recoverable machine check errors or other unrecoverable internal errors.
  • Page 66: Processor Power Signals

    Signal Description 6.11 Processor Power Signals Table 6-13. Processor Power Signals Direction/ Signal Name Description Buffer Type Processor core power rail VCCIO Processor power for I/O VDDQ Processor I/O supply voltage for DDR3 VAXG Graphics core power supply. VCCPLL VCCPLL provides isolated power for internal processor PLLs VCCSA System Agent power supply VIDALERT#, VIDSCLK, and VIDSCLK comprise a three signal serial...
  • Page 67: Processor Internal Pull Up/Pull Down

    Signal Description 6.14 Processor Internal Pull Up/Pull Down Table 6-16. Processor Internal Pull Up/Pull Down Signal Name Pull Up/Pull Down Rail Value BPM[7:0] Pull Up VCCIO 65–165  PRDY# Pull Up VCCIO 65–165  PREQ# Pull Up VCCIO 65–165  Pull Down 5–15 k...
  • Page 68 Signal Description Datasheet, Volume 1...
  • Page 69: Electrical Specifications

    Electrical Specifications Electrical Specifications Power and Ground Lands The processor has V and V (ground) inputs for DDQ, CCPLL, CCAXG, on-chip power distribution. All power lands must be connected to their respective processor power planes, while all VSS lands must be connected to the system ground plane.
  • Page 70: Processor Clocking (Bclk[0], Bclk#[0])

    Electrical Specifications Processor Clocking (BCLK[0], BCLK#[0]) The processor uses a differential clock to generate the processor core operating frequency, memory controller frequency, system agent frequencies, and other internal clocks. The processor core frequency is determined by multiplying the processor core ratio by the BCLK frequency.
  • Page 71: Vr 12.0 Voltage Identification Definition

    Electrical Specifications Table 7-1. VR 12.0 Voltage Identification Definition (Sheet 1 of 3) CC_MAX CC_MAX 0.00000 0.88500 0.25000 0.89000 0.25500 0.89500 0.26000 0.90000 0.26500 0.90500 0.27000 0.91000 0.27500 0.91500 0.28000 0.92000 0.28500 0.92500 0.29000 0.93000 0.29500 0.93500 0.30000 0.94000 0.30500 0.94500 0.31000 0.95000...
  • Page 72 Electrical Specifications Table 7-1. VR 12.0 Voltage Identification Definition (Sheet 2 of 3) CC_MAX CC_MAX 0.45500 1.09500 0.46000 1.10000 0.46500 1.10500 0.47000 1.11000 0.47500 1.11500 0.48000 1.12000 0.48500 1.12500 0.49000 1.13000 0.49500 1.13500 0.50000 1.14000 0.50500 1.14500 0.51000 1.15000 0.51500 1.15500 0.52000 1.16000...
  • Page 73 Electrical Specifications Table 7-1. VR 12.0 Voltage Identification Definition (Sheet 3 of 3) CC_MAX CC_MAX 0.67000 1.31000 0.67500 1.31500 0.68000 1.32000 0.68500 1.32500 0.69000 1.33000 0.69500 1.33500 0.70000 1.34000 0.70500 1.34500 0.71000 1.35000 0.71500 1.35500 0.72000 1.36000 0.72500 1.36500 0.73000 1.37000 0.73500 1.37500...
  • Page 74: System Agent (Sa) Vcc Vid

    Future Intel processors Note 1 Notes: Some of V configurations are reserved for future Intel processor families. CCSA Reserved or Unused Signals The following are the general types of reserved (RSVD) signals and connection guidelines: • RSVD – These signals should not be connected.
  • Page 75: Signal Groups

    Electrical Specifications Signal Groups Signals are grouped by buffer type and similar characteristics as listed in Table 7-3. The buffer type indicates which signaling technology and specifications apply to the signals. All the differential signals, and selected DDR3 and Control Sideband signals have On- Die Termination (ODT) resistors.
  • Page 76: Test Access Port (Tap) Connection

    Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, Intel recommends the processor be first in the TAP chain, followed by any other components within the system. A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage.
  • Page 77: Storage Conditions Specifications

    JESD22-A103 (high temp) standards when applicable for volatile memory. Intel branded products are specified and certified to meet the following temperature and humidity limits that are given as an example only (Non-Operating Temperature Limit: -40 °C to 70 °C and Humidity: 50% to 90%, non-condensing with a maximum wet bulb of 28 °C.) Post board attach storage temperature limits...
  • Page 78: Dc Specifications

    Electrical Specifications 7.10 DC Specifications The processor DC specifications in this section are defined at the processor pads, unless noted otherwise. See Chapter 8 for the processor land listings and Chapter 6 for signal definitions. Voltage and current specifications are detailed in Table 7-5, Table...
  • Page 79 VID range. Note that this differs from the VID employed by the processor during a power management event (Adaptive Thermal Monitor, Enhanced Intel SpeedStep Technology, or Low Power States). The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with a 20-MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1-M...
  • Page 80: Processor System Agent I/O Buffer Supply Dc Voltage And Current Specifications

    Electrical Specifications Table 7-6. Processor System Agent I/O Buffer Supply DC Voltage and Current Specifications Symbol Parameter Unit Note Voltage for the system agent 0.879 0.925 0.971 CCSA Processor I/O supply voltage for 1.425 1.575 DDR3 PLL supply voltage (DC + AC 1.71 1.89 CCPLL...
  • Page 81: Processor Graphics Vid Based (Vaxg) Supply Dc Voltage And Current Specifications

    VID range. Note that this differs from the VID employed by the processor during a power management event (Adaptive Thermal Monitor, Enhanced Intel SpeedStep Technology, or Low Power States). Table 7-8.
  • Page 82: Control Sideband And Tap Signal Group Dc Specifications

    Electrical Specifications Table 7-8. DDR3 Signal Group DC Specifications (Sheet 2 of 2) Symbol Parameter Units Notes DDR3 command buffer pull-up Ω ON_UP(CMD) resistance DDR3 command buffer pull- Ω ON_DN(CMD) down resistance DDR3 control buffer pull-up Ω ON_UP(CTL) resistance DDR3 control buffer pull-down Ω...
  • Page 83: Pcie Dc Specifications

    Electrical Specifications Table 7-10. PCIe DC Specifications 1,11 Symbol Parameter Units Notes Low differential peak to peak Tx voltage TX-DIFF-p-p Low swing Differential peak to peak Tx voltage swing TX-DIFF-p-p Tx AC Peak Common Mode Output — — 1, 2, 6 TX_CM-AC-p Voltage (Gen1 only) Tx AC Peak Common Mode Output...
  • Page 84: Platform Environmental Control Interface (Peci) Dc Specifications

    Platform Environmental Control Interface (PECI) DC Specifications PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external thermal monitoring devices. The processor contains a Digital Thermal Sensor (DTS) that reports a relative die temperature as an offset from Thermal Control Circuit (TCC) activation temperature.
  • Page 85: Dc Characteristics

    Electrical Specifications 7.11.2 DC Characteristics The PECI interface operates at a nominal voltage set by V . The set of DC electrical CCIO specifications shown in Table 7-11 is used with devices normally operating from a V CCIO interface supply. V nominal levels will vary between processor families.
  • Page 86 Electrical Specifications Datasheet, Volume 1...
  • Page 87: Processor Pin And Signal Information

    Processor Pin and Signal Information Processor Pin and Signal Information Processor Pin Assignments The processor pinmap quadrants are shown in Figure 8-1 through Figure 8-4. Table 8-1 provides a listing of all processor pins ordered alphabetically by pin name. Note: Pin names SA_ECC_CB[7:0] and SB_ECC_CB[7:0] are RSVD on desktop processors.
  • Page 88: Socket Pinmap (Top View, Upper-Left Quadrant)

    Processor Pin and Signal Information Figure 8-1. Socket Pinmap (Top View, Upper-Left Quadrant) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VDDQ VDDQ VDDQ SA_BS[0] SA_CK[ 0] SA_M A[1] VSS_NCTF SA_DQ[37] SA_CK#[2]...
  • Page 89: Socket Pinmap (Top View, Upper-Right Quadrant)

    Processor Pin and Signal Information Figure 8-2. Socket Pinmap (Top View, Upper-Right Quadrant) 20 19 18 17 16 15 14 13 12 11 10 RSVD SB_CKE[1] SB_ MA[9 ] SB_ MA[1 4 ] SA_ECC_CB[3] SA_ECC_CB[6] SA_ DQ[3 1 ] SA_ DQ[2 4 ] SA_ DQ[2 3 ] RSVD_ NCTF VSS VSS...
  • Page 90: Socket Pinmap (Top View, Lower-Left Quadrant)

    Processor Pin and Signal Information Figure 8-3. Socket Pinmap (Top View, Lower-Left Quadrant) VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VSS VSS VSS VSS VSS VSS VSS VSS VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG RSVD RSVD...
  • Page 91: Socket Pinmap (Top View, Lower-Right Quadrant)

    Processor Pin and Signal Information Figure 8-4. Socket Pinmap (Top View, Lower-Right Quadrant) DMI_RX[2] DMI_ TX#[2 ] DMI_ TX[2 ] DM I_RX#[2] VCCIO DMI_RX[0] BCLK[0] BCLK#[0] DMI_ TX#[1 ] DMI_ TX[1 ] DM I_RX#[0] VSS VSS VCCIO DMI_RX[1] DMI_ TX[0 ] DMI_ TX#[0 ] DM I_RX#[1] VCCIO VCCIO VCCIO...
  • Page 92: Processor Pin List By Pin Name

    Processor Pin and Signal Information Table 8-1. Processor Pin List by Pin Table 8-1. Processor Pin List by Pin Name Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. BCLK_ITP Diff Clk DMI_TX#[0] BCLK_ITP# Diff Clk DMI_TX#[1] BCLK[0]...
  • Page 93 Processor Pin and Signal Information Table 8-1. Processor Pin List by Pin Table 8-1. Processor Pin List by Pin Name Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. PE_TX[2] PCI Express PEG_TX[2] PCI Express PE_TX[3] PCI Express PEG_TX[3]...
  • Page 94 Processor Pin and Signal Information Table 8-1. Processor Pin List by Pin Table 8-1. Processor Pin List by Pin Name Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. RSVD AJ30 SA_BS[2] AV20 DDR3 RSVD AJ31 SA_CAS#...
  • Page 95 Processor Pin and Signal Information Table 8-1. Processor Pin List by Pin Table 8-1. Processor Pin List by Pin Name Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. SA_DQ[26] DDR3 SA_DQS[6] AK38 DDR3 SA_DQ[27] DDR3 SA_DQS[7]...
  • Page 96 Processor Pin and Signal Information Table 8-1. Processor Pin List by Pin Table 8-1. Processor Pin List by Pin Name Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. SB_BS[2] AW17 DDR3 SB_DQ[26] AR13 DDR3 SB_CAS# AK25...
  • Page 97 Processor Pin and Signal Information Table 8-1. Processor Pin List by Pin Table 8-1. Processor Pin List by Pin Name Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. SB_DQS[6] AL33 DDR3 SM_DRAMRST# AW18 DDR3 SB_DQS[7] AG35...
  • Page 98 Processor Pin and Signal Information Table 8-1. Processor Pin List by Pin Table 8-1. Processor Pin List by Pin Name Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. Datasheet, Volume 1...
  • Page 99 Processor Pin and Signal Information Table 8-1. Processor Pin List by Pin Table 8-1. Processor Pin List by Pin Name Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. VCCAXG AB38 VCCAXG AB39 VCCAXG AB40 VCCAXG AC33...
  • Page 100 Processor Pin and Signal Information Table 8-1. Processor Pin List by Pin Table 8-1. Processor Pin List by Pin Name Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. VCCIO VCCPLL AK12 VCCIO AG33 VCCSA VCCIO AJ16...
  • Page 101 Processor Pin and Signal Information Table 8-1. Processor Pin List by Pin Table 8-1. Processor Pin List by Pin Name Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. AJ25 AA33 AJ27 AA34 AJ36 AA35 AA36 AA37...
  • Page 102 Processor Pin and Signal Information Table 8-1. Processor Pin List by Pin Table 8-1. Processor Pin List by Pin Name Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. AM30 AR18 AM36 AR19 AM37 AR27 AM38 AR30...
  • Page 103 Processor Pin and Signal Information Table 8-1. Processor Pin List by Pin Table 8-1. Processor Pin List by Pin Name Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. AV11 AV14 AV17 AV35 AV38 AW10 AW11 AW14...
  • Page 104 Processor Pin and Signal Information Table 8-1. Processor Pin List by Pin Table 8-1. Processor Pin List by Pin Name Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. Datasheet, Volume 1...
  • Page 105 Processor Pin and Signal Information Table 8-1. Processor Pin List by Pin Name Pin Name Pin # Buffer Type Dir. VSS_NCTF VSS_NCTF AV39 VSS_NCTF AY37 VSS_NCTF VSS_SENSE Analog VSSAXG_SENSE Analog VSSIO_SENSE Analog § § Datasheet, Volume 1...
  • Page 106 Processor Pin and Signal Information Datasheet, Volume 1...
  • Page 107: Ddr Data Swizzling

    DDR Data Swizzling DDR Data Swizzling To achieve better memory performance and better memory timing, Intel design performed the DDR Data pin swizzeling that will allow a better use of the product across different platforms. Swizzeling has no effect on functional operation and is invisible to the OS/SW.
  • Page 108: Ddr Data Swizzling Table - Channel A

    DDR Data Swizzling Table 9-1. DDR Data Swizzling Table 9-1. DDR Data Swizzling Table – Channel A Table – Channel A Pin Name Pin # MC Pin Name Pin Name Pin # MC Pin Name SA_DQ[0] DQ01 SA_DQ[46] AN39 DQ46 SA_DQ[1] DQ02 SA_DQ[47]...
  • Page 109: Ddr Data Swizzling Table - Channle B

    DDR Data Swizzling Table 9-2. DDR Data Swizzling Table 9-2. DDR Data Swizzling Table – Channle B Table – Channle B Pin Name Pin # MC Pin Name Pin Name Pin # MC Pin Name SB_DQ[0] DQ03 SB_DQ[46] AR35 DQ47 SB_DQ[1] DQ02 SB_DQ[47]...
  • Page 110 DDR Data Swizzling Datasheet, Volume 1...