Flash Interface Registers; Flash Access Control Register (Flash_Acr) - ST STM32F412 Reference Manual

Embedded Flash memory interface
3.8

Flash interface registers

3.8.1

Flash access control register (FLASH_ACR)

The Flash access control register is used to enable/disable the acceleration features and
control the Flash memory access time according to CPU frequency.
Address offset: 0x00
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. DCRST ICRST
rw
Bits 31:13 Reserved, must be kept cleared.
Bit 12 DCRST: Data cache reset
Bit 11 ICRST: Instruction cache reset
Bit 10 DCEN: Data cache enable
Bit 9 ICEN: Instruction cache enable
Bit 8 PRFTEN: Prefetch enable
Bits 7:4 Reserved, must be kept cleared.
Bits 3:0 LATENCY: Latency
74/1163
27 26 25
Res. Res. Res.
11 10 9
DCEN ICEN
w rw rw
0: Data cache is not reset
1: Data cache is reset
This bit can be written only when the D cache is disabled.
0: Instruction cache is not reset
1: Instruction cache is reset
This bit can be written only when the I cache is disabled.
0: Data cache is disabled
1: Data cache is enabled
0: Instruction cache is disabled
1: Instruction cache is enabled
0: Prefetch is disabled
1: Prefetch is enabled
These bits represent the ratio of the CPU clock period to the Flash memory access time.
0000: Zero wait state
0001: One wait state
0010: Two wait states
-
-
-
1110: Fourteen wait states
1111: Fifteen wait states
24 23 22
Res. Res. Res.
8 7 6
PRFTEN Res. Res.
rw
RM0402 Rev 6
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. Res. LATENCY
rw rw
RM0402
17 16
Res. Res.
1 0
rw rw