Dma Stream X Number Of Data Register (Dma_Sxndtr) - ST STM32F423 Reference Manual

RM0430
Bit 2 TEIE: transfer error interrupt enable
Bit 1 DMEIE: direct mode error interrupt enable
Bit 0 EN: stream enable / flag stream ready when read low
Note: Before setting EN bit to '1' to start a new transfer, the event flags corresponding to the
9.5.6

DMA stream x number of data register (DMA_SxNDTR)

Address offset: 0x14 + 0x18 * x, (x = 0 to 7)
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 NDT[15:0]: number of data items to transfer (0 up to 65535)
This bit is set and cleared by software.
0: TE interrupt disabled
1: TE interrupt enabled
This bit is set and cleared by software.
0: DME interrupt disabled
1: DME interrupt enabled
This bit is set and cleared by software.
0: stream disabled
1: stream enabled
This bit may be cleared by hardware:
– on a DMA end of transfer (stream ready to be configured)
– if a transfer error occurs on the AHB master buses
– when the FIFO threshold on memory AHB port is not compatible with the size of the
burst
When this bit is read as 0, the software is allowed to program the configuration and FIFO bits
registers. It is forbidden to write these registers when the EN bit is read as 1.
stream in DMA_LISR or DMA_HISR register must be cleared.
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
This register can be written only when the stream is disabled. When the stream is enabled,
this register is read-only, indicating the remaining data items to be transmitted. This register
decrements after each DMA transfer.
Once the transfer is completed, this register can either stay at zero (when the stream is in
normal mode) or be reloaded automatically with the previously programmed value in the
following cases:
– when the stream is configured in circular mode.
– when the stream is enabled again by setting EN bit to '1'.
If the value of this register is zero, no transaction can be served even if the stream is
enabled.
Direct memory access controller (DMA)
24 23 22
Res. Res. Res.
8 7 6
NDT[15:0]
rw rw rw
RM0430 Rev 8
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
rw rw rw rw
17 16
Res. Res.
1 0
rw rw
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