Rcc Ahb2 Peripheral Clock Enable In Low Power Mode Register (Rcc_Ahb2Lpenr); Rcc Ahb3 Peripheral Clock Enable In Low Power Mode Register (Rcc_Ahb3Lpenr) - ST STM32F412 Reference Manual

Advanced arm-based 32-bit mcus

Table of Contents

Reset and clock control (RCC) for STM32F412xx

RCC AHB2 peripheral clock enable in low power mode register

(RCC_AHB2LPENR)

Address offset: 0x54

Reset value: 0x0000 00C0

Access: no wait state, word, half-word and byte access.

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 OTGFSLPEN: USB OTG FS clock enable during Sleep mode

Bit 6 RNGLPEN: RNG clock enable during Sleep mode

Bits 5:0 Reserved, must be kept at reset value.

RCC AHB3 peripheral clock enable in low power mode register

(RCC_AHB3LPENR)

Address offset: 0x58

Reset value: 0x0000 0003

Access: no wait state, word, half-word and byte access.

Set and cleared by software.

0: USB OTG FS clock disabled during Sleep mode

1: USB OTG FS clock enabled during Sleep mode

Set and cleared by software.

0: RNG clock disabled during Sleep mode

1: RNG clock enabled during Sleep mode

RM0402 Rev 6

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