Rcc Ahb3 Peripheral Clock Enable In Low Power Mode Register (Rcc_Ahb3Lpenr) - ST STM32F205 series Reference Manual

RM0033
Bit 5 HASHLPEN: Hash modules clock enable during Sleep mode
Bit 4 CRYPLPEN: Cryptography modules clock enable during Sleep mode
Bit 3:1
Bit 0 DCMILPEN: Camera interface enable during Sleep mode
5.3.17 RCC AHB3 peripheral clock enable in low power mode register
(RCC_AHB3LPENR)
Address offset: 0x58
Reset value: 0x0000 0001
Access: no wait state, word, half-word and byte access.
31 30 29
15 14 13
Bits 31:1 Reserved, always read as 0.
FSMCLPEN: Flexible static memory controller module clock enable during Sleep mode
Set and cleared by software.
Bit 0
0: FSMC module clock disabled during Sleep mode
1: FSMC module clock enabled during Sleep mode
Set and cleared by software.
0: Hash modules clock disabled during Sleep mode
1: Hash modules clock enabled during Sleep mode
Set and cleared by software.
0: cryptography modules clock disabled during Sleep mode
1: cryptography modules clock enabled during Sleep mode
Reserved, always read as 0
Set and cleared by software.
0: Camera interface clock disabled during Sleep mode
1: Camera interface clock enabled during Sleep mode
28 27 26 25
12 11 10 9
24 23 22
Reserved
8 7 6
Reserved
RM0033 Rev 8
Reset and clock control (RCC)
21 20 19 18
5 4 3 2
17 16
1 0
FSMC
LPEN
rw
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