Access State Control Register (Astcr) - Hitachi H8S/2215 Series Hardware Manual

ABWCR sets the data bus width for the external memory space. The bus width for on-chip
memory and internal I/O registers except for the on-chip USB is fixed regardless of the settings in
ABWCR.
Bit Bit Name Initial Value R/W
7 ABW7 1/0*
2
6 ABW6* 1/0*
5 ABW5 1/0*
4 ABW4 1/0*
3 ABW3 1/0*
2 ABW2 1/0*
1 ABW1 1/0*
0 ABW0 1/0*
Notes: *1 In modes 5 to 7, initial value of each bit is 1. In mode 4, initial value of each bit is 0.
*2 The on-chip USB is allocated to area 6. Therefore this bit should be set to 1.
6.3.2

Access State Control Register (ASTCR)

ASTCR designates each area as either a 2-state access space or a 3-state access space.
ASTCR sets the number of access states for the external memory space. The number of access
states for on-chip memory and internal I/O registers except for the on-chip USB is fixed regardless
of the settings in ASTCR.
Bit Bit Name Initial Value R/W
7 AST7 1
6 AST6* 1
5 AST5 1
4 AST4 1
3 AST3 1
2 AST2 1
1 AST1 1
0 AST0 1
Note: * The on-chip USB is allocated to area 6. Therefore this bit should be set to 1.
Rev. 3.0, 10/02, page 102 of 686
Description
1
R/W Area 7 to 0 Bus Width Controls:
1
R/W These bits select whether the corresponding area is to
be designated for 8-bit access or 16-bit access.
1
R/W
0: Area n is designated for 16-bit access
1
R/W
1: Area n is designated for 8-bit access
1
R/W
Legend
1
R/W
1
R/W
1
R/W
Description
R/W Area 7 to 0 Access State Controls:
R/W These bits select whether the corresponding area is to
be designated as a 2-state access space or a 3-state
R/W
access space. Wait state insertion is enabled or disabled
R/W
at the same time.
R/W
0: Area n is designated for 2-state access
R/W
R/W
1: Area n is designated for 3-state access
R/W
Legend
n = 7 to 0
Wait state insertion in area n external space is
disabled
Wait state insertion in area n external space is
enabled
n = 7 to 0