Figure 10.42 Timing For Status Flag Clearing By Cpu; Figure 10.43 Timing For Status Flag Clearing By Dtc Activation - Hitachi H8S/2628 Hardware Manual

Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DTC is activated, the flag is cleared automatically. Figure 10.42 shows the
timing for status flag clearing by the CPU, and figure 10.43 shows the timing for status flag
clearing by the DTC.
φ
Address
Write signal
Status flag
Interrupt
request
signal

Figure 10.42 Timing for Status Flag Clearing by CPU

φ
Address
Status flag
Interrupt
request
signal

Figure 10.43 Timing for Status Flag Clearing by DTC Activation

Rev. 1.0, 09/02, page 230 of 568
TSR write cycle
T1 T2
TSR address
DTC DTC
read cycle write cycle
T1 T2 T1
Destination
Source address
address
T2