Timing Of Status Flag Setting; Figure 9.13 Timing Of Input Capture Input Signal; Figure 9.14 Cmf Flag Setting Timing When Compare Match Occurs - Hitachi H8/3062 Hardware Manual

φ
Input capture input
Input capture signal
8TCNT N
TCORB N

Figure 9.13 Timing of Input Capture Input Signal

9.4.4

Timing of Status Flag Setting

Timing of CMFA/CMFB Flag Setting when Compare Match Occurs: The CMFA and CMFB
flags in 8TCSR are set to 1 by the compare match signal output when the TCORA or TCORB and
8TCNT values match. The compare match signal is generated in the last state of the match (when
the matched 8TCNT count value is updated). Therefore, after the 8TCNT and TCORA or
TCORB values match, the compare match signal is not generated until an incrementing clock
pulse signal is generated. Figure 9.14 shows the timing in this case.
φ
8TCNT N N+1
TCOR
N
Compare match signal
CMF

Figure 9.14 CMF Flag Setting Timing when Compare Match Occurs

Timing of CMFB Flag Setting when Input Capture Occurs: On generation of an input capture
signal, the CMFB flag is set to 1 and at the same time the 8TCNT value is transferred to TCORB.
Figure 9.15 shows the timing in this case.
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