Timing Of Imfa To Imfd Flag Setting At Compare Match - Hitachi H8/3672 Series Hardware Manual

φ
Input capture
signal
TCNT
GRA, GRB
GRC, GRD
Figure 11-20 Buffer Operation Timing (Input Capture)
11.5.6

Timing of IMFA to IMFD Flag Setting at Compare Match

If a general register (GRA, GRB, GRC, or GRD) is used as an output compare register, the
corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when TCNT matches the general
register. The compare match signal is generated in the last state in which the values match (when
TCNT is updated from the matching count to the next count). Therefore, when TCNT matches a
general register, the compare match signal is generated only after the next TCNT clock pulse is
input. Figure 11-21 shows the timing of the IMFA to IMFD flag setting at compare match.
φ
TCNT input
clock
TCNT
GRA to GRD
Compare
match signal
IMFA to IMFD
IRRTW
Figure 11-21 Timing of IMFA to IMFD Flag Setting at Compare Match
N N+1
M N
M
N N+1
N
N+1
N
Rev. 1.0, 03/01, page 145 of 280