Figure 10.41 Tciu Interrupt Setting Timing; Figure 10.42 Timing For Status Flag Clearing By Cpu - Hitachi H8S/2215 Series Hardware Manual

φ
TCNT
input clock
TCNT
(underflow)
Underflow
signal
TCFU flag
TCIU interrupt
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DTC or DMAC is activated, the flag is cleared automatically. Figure 10.42 shows
the timing for status flag clearing by the CPU, and figure 10.43 shows the timing for status flag
clearing by the DTC or DMAC.
Address
Write signal
Status flag
Interrupt
request
signal

Figure 10.42 Timing for Status Flag Clearing by CPU

Rev. 3.0, 10/02, page 318 of 686
H'0000

Figure 10.41 TCIU Interrupt Setting Timing

TSR write cycle
H'FFFF
T1 T2
TSR address