Timing Of Tcnt External Reset; Timing Of Overflow Flag (Ovf) Setting - Hitachi H8S/2338 Series Hardware Manual

9.3.3

Timing of TCNT External Reset

TCNT is cleared at the rising edge of an external reset input, depending on the settings of the
CCLR1 and CCLR0 bits in TCR. The clear pulse width must be at least 1.5 states. Figure 9-7
shows the timing of this operation.
ø
External reset
input pin
Clear signal
TCNT
9.3.4

Timing of Overflow Flag (OVF) Setting

The OVF in TCSR is set to 1 when TCNT overflows (changes from H'FF to H'00). Figure 9-8
shows the timing of this operation.
ø
TCNT
Overflow signal
OVF
360
N–1
Figure 9-7 Timing of Clearance by External Reset
H'FF
Figure 9-8 Timing of OVF Setting
N H'00
H'00