Timer Output Compare Control Register (Tocr) - Hitachi SH7095 Hardware User Manual

• Bits 6 to 2: Reserved. These bits always read 0. The write value should always be 0.Do not
write 1.
• Bits 1 and 0: Clock selects (CKS1, CKS0). These bits select whether to use an external clock
or one of the three internal clocks input to FRC. The external clock is counted from the rising
edge.
Bit 1 (CKS1) Bit 0 (CKS0)
0 0
1
1 0
1
11.2.7

Timer Output Compare Control Register (TOCR)

Bit:
Bit name:
Initial value:
R/W:
The TOCR is an 8-bit read/write register that selects the output level for output compare, enables
output compare output, and controls switching between access of output compare registers A and
B. TOCR is initialized to H'E0 by resets, in the standby mode and by module standby function is
used.
Bits 7 to 5: Reserved. These bits always read 1. The write value should always be 1. Do not write
0.
Bit 4: Output compare register select (OCRS). These bits share the same address as OCRA and
OCRB. The OCRS bit controls which register is selected when reading/writing to this address. It
does not affect the operation of OCRA and OCRB.
Bit 4 (OCRS)
0
1
Description
Internal clock: count at φ/8 (initial value)
Internal clock: count at φ/32
Internal clock: count at φ/128
External clock: count at rise edge
7 6
— — —
1 1
— — —
Description
Selects OCRA register (initial value)
Selects OCRB register
5 4 3
OCRS —
1 0 0
R/W R/W
2 1
— OLVLA OLVLB
0 0
R/W R/W R/W
Hitachi 293
0
0