Timer Output Compare Control Register (Tocr)-H'ff97 - Hitachi H8/329 Series Hardware Manual

Bit 1 Bit 0
CKS1 CKS0
0 0
0 1
1 0
1 1
6.2.7 Timer Output Compare Control Register (TOCR)—H'FF97
Bit 7
—
Initial value 1
Read/Write —
The TOCR is an 8-bit readable/writable register that controls the output compare function.
The TOCR is initialized to H'E0 at a reset and in the standby modes.
Bits 7 to 5—Reserved: These bits cannot be modified and are always read as "1."
Bit 4—Output Compare Register Select (OCRS): When the CPU accesses addresses H'FF94
and H'FF95, this bit directs the access to either OCRA or OCRB. These two registers share the
same addresses as follows:
Upper byte of OCRA and upper byte of OCRB: H'FF94
Lower byte of OCRA and lower byte of OCRB: H'FF95
Bit 4
OCRS Description
0 The CPU can access OCRA.
1 The CPU can access OCRB.
Bit 3—Output Enable A (OEA): This bit enables or disables output of the output compare A
signal (FTOA).
Bit 3
OEA Description
0 Output compare A output is disabled.
1 Output compare A output is enabled.
Description
Ø/2 Internal clock source
Ø/8 Internal clock source
Ø/32 Internal clock source
External clock source (rising edge)
6 5
— —
1 1
— —
4 3
OCRS OEA OEB
0 0
R/W R/W R/W
127
(Initial value)
2 1 0
OLVLA OLVLB
0 0 0
R/W R/W
(Initial value)
(Initial value)