Timer I/O Control Register (Tior) - Hitachi H8/3062 Hardware Manual

Single-chip microcomputer

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When bit TPSC2 is cleared to 0 an internal clock source is selected, and the timer counts only

falling edges. When bit TPSC2 is set to 1 an external clock source is selected, and the timer counts

the edges selected by bits CKEG1 and CKEG0.

When channel 2 is set to phase counting mode (MDF = 1 in TMDR), the settings of bits TPSC2 to

TPSC0 in 16TCR2 are ignored. Phase counting takes precedence.

Timer I/O Control Register (TIOR)

TIOR is an 8-bit register. The 16-bit timer has three TIORs, one in each channel.

Channel Abbreviation Function

Initial value

Reserved bit

Each TIOR is an 8-bit readable/writable register that selects the output compare or input capture

function for GRA and GRB, and specifies the functions of the TIORA and TIORB pins. If the

output compare function is selected, TIOR also selects the type of output. If input capture is

selected, TIOR also selects the edges of the input capture signal.

TIOR is initialized to H'88 by a reset and in standby mode.

Bit 7—Reserved: This bit cannot be modified and is always read as 1.

TIOR controls the general registers. Some functions differ in PWM

I/O control B2 to B0

These bits select GRB functions

Reserved bit

I/O control A2 to A0

These bits select GRA