Timer I/O Control Register (Tior); Table 10.8 Md3 To Md0 - Hitachi H8S/2215 Series Hardware Manual

Table 10.8 MD3 to MD0

Bit 3 Bit2
1 2
MD3* MD2*
0 0
1
×
1
Legend: x: Don't care
Notes: *1 MD3 is reserved bit. In a write, it should be written with 0.
*2 Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always
be written to MD2.
10.3.3

Timer I/O Control Register (TIOR)

The TIOR registers control the TGR registers. The TPU has eight TIOR registers, two each for
channel 0, and one each for channels 1 and 2. Care is required since TIOR is affected by the
TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST
bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the
counter is cleared to 0 is specified. When TGRC or TGRD is designated for buffer operation, this
setting is invalid and the register operates as a buffer register.
• • • • TIORH_0, TIOR_1, TIOR_2
Bit Bit Name Initial value
7 IOB3 0
6 IOB2 0
5 IOB1 0
4 IOB0 0
3 IOA3 0
2 IOA2 0
1 IOA1 0
0 IOA0 0
Rev. 3.0, 10/02, page 274 of 686
Bit 1 Bit 0
MD1 MD0
0 0
1
1 0
1
0 0
1
1 0
1
× ×
R/W Description
R/W I/O Control B3 to B0
R/W Specify the function of TGRB.
R/W
R/W
R/W I/O Control A3 to A0
R/W Specify the function of TGRA.
R/W
R/W
Description
Normal operation
Reserved
PWM mode 1
PWM mode 2
Phase counting mode 1
Phase counting mode 2
Phase counting mode 3
Phase counting mode 4
–