Timer I/O Control Register (Tior) - Hitachi H8/3032 Series Hardware Manual

Bits 2 to 0—Timer Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the counter clock
source.
Bit 2
TPSC2
0
1
When bit TPSC2 is cleared to 0 an internal clock source is selected, and the timer counts only
falling edges. When bit TPSC2 is set to 1 an external clock source is selected, and the timer
counts the edge or edges selected by bits CKEG1 and CKEG0.
When channel 2 is set to phase counting mode (MDF = 1 in TMDR), the settings of bits TPSC2 to
TPSC0 in TCR2 are ignored. Phase counting takes precedence.

8.2.11 Timer I/O Control Register (TIOR)

TIOR is an 8-bit register. The ITU has five TIORs, one in each channel.
Channel
0
1
2
3
4
Downloaded from Elcodis.com electronic components distributor
Bit 1 Bit 0
TPSC1 TPSC0 Function
0 0 Internal clock: ø
1 Internal clock: ø/2
1 0 Internal clock: ø/4
1 Internal clock: ø/8
0 0 External clock A: TCLKA input
1 External clock B: TCLKB input
1 0 External clock C: TCLKC input
1 External clock D: TCLKD input
Abbreviation Function
TIOR0 TIOR controls the general registers. Some functions differ in PWM
mode. TIOR3 and TIOR4 settings are ignored when complementary
TIOR1
PWM mode or reset-synchronized PWM mode is selected in
TIOR2
channels 3 and 4.
TIOR3
TIOR4
198
(Initial value)