Timer I/O Control Register (Tior) - Hitachi H8/3035 Series Hardware Manual

When bit TPSC2 is cleared to 0 an internal clock source is selected, and the timer counts only
falling edges. When bit TPSC2 is set to 1 an external clock source is selected, and the timer
counts the edge or edges selected by bits CKEG1 and CKEG0.
When channel 2 is set to phase counting mode (MDF = 1 in TMDR), the settings of bits TPSC2
to TPSC0 in TCR2 are ignored. Phase counting takes precedence.

8.2.11 Timer I/O Control Register (TIOR)

TIOR is an 8-bit register. The ITU has five TIORs, one in each channel.
Channel Abbreviation Function
0 TIOR0
1 TIOR1
2 TIOR2
3 TIOR3
4 TIOR4
Bit 7
—
Initial value 1
Read/Write —
Reserved bit
Each TIOR is an 8-bit readable/writable register that selects the output compare or input capture
function for GRA and GRB, and specifies the functions of the TIOCA and TIOCB pins. If the
output compare function is selected, TIOR also selects the type of output. If input capture is
selected, TIOR also selects the edge or edges of the input capture signal.
TIOR is initialized to H'88 by a reset and in standby mode.
TIOR controls general registers. Some functions differ in PWM mode.
TIOR3 and TIOR4 settings are ignored when complementary PWM
mode or reset-synchronized PWM mode is selected in channels 3 and
4.
6 5
IOB2 IOB1 IOB0
0 0
R/W R/W R/W
I/O control B2 to B0
These bits select GRB functions
4 3 2
— IOA2
0 1 0
— R/W
I/O control A2 to A0
These bits select GRA
functions
Reserved bit
1 0
IOA1 IOA0
0 0
R/W R/W
189