Serial Control Register (Scr) - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

Bit Bit Name
3 BCP1
2 BCP0
1 CKS1
0 CKS0
15.3.6

Serial Control Register (SCR)

SCR performs enabling or disabling of SCI transfer operations and interrupt requests, and
selection of the transfer/receive clock source. For details on interrupt requests, refer to section
15.9, Interrupts. Some bit functions of SCR differ in normal serial communication interface mode
and Smart Card interface mode.
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
Description
Basic Clock Pulse 1 and 0
These bits select the number of basic clock
periods in a 1-bit transfer interval on the Smart
Card interface.
00: 32 clock (S = 32)
01: 64 clock (S = 64)
10: 372 clock (S = 372)
11: 256 clock (S = 256)
For details, refer to section 15.7.4, Receive Data
Sampling Timing and Reception Margin. S stands
for the value of S in BRR (see section 15.3.9, Bit
Rate Register (BRR)).
Clock Select 1 and 0:
These bits select the clock source for the on-chip
baud rate generator.
00: ø clock (n = 0)
01: ø/4 clock (n = 1)
10: ø/16 clock (n = 2)
11: ø/64 clock (n = 3)
For the relation between the bit rate register
setting and the baud rate, see section 15.3.9, Bit
Rate Register (BRR). n is the decimal display of
the value of n in BRR (see section 15.3.9, Bit Rate
Register (BRR)).
Rev. 1.0, 09/01, page 633 of 904