Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 730

When there is no parity error
When a parity error occurs
Legend
Ds
D0 to D7
Dp
DE
Figure 15.22 Normal Smart Card Interface Data Format
Data transfer with the types of IC cards (direct convention and inverse convention) are performed
as described in the following.
(Z)
Figure 15.23 Direct Convention (SDIR = SINV = O/( ( ( ( = 0)
As in the above sample start character, with the direct convention type, the logic 1 level
corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order.
The start character data above is H'3B. For the direct convention type, clear the SDIR and SINV
bits in SCMR to 0. According to the Smart Card regulations, clear the O/( bit in SMR to 0 to
select even parity mode.
(Z)
Figure 15.24 Inverse Convention (SDIR = SINV = O/( ( ( ( = 1)
With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to
state Z, and transfer is performed in MSB-first order. The start character data above is H'3F. For
the inverse convention type, set the SDIR and SINV bits in SCMR to 1. According to the Smart
Card regulations, even parity mode is the logic 0 level of the parity bit, and corresponds to state Z.
In this LSI, the SINV bit inverts only data bits D7 to D0. Therefore, set the O/( bit in SMR to 1
to invert the parity bit for both transmission and reception.
Rev. 1.0, 09/01, page 686 of 904
Ds D0 D1 D2
Transmitting station output
Ds D0 D1 D2
Transmitting station output
: Start bit
: Data bits
: Parity bit
: Error signal
A Z Z A Z
Ds D0 D1 D2 D3
A Z Z A A
Ds D7 D6 D5 D4
D3 D4 D5 D6
D3 D4 D5 D6
Z Z A A
D4 D5 D6 D7 Dp
A A A A
D3 D2 D1 D0 Dp
D7 Dp
D7 Dp DE
Receiving station
output
Z (Z) State
Z (Z) State