Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 303

Bit Bit Name
11 DTA1
10 —
Initial Value R/W
0 R/W
0 R/W
Description
Data Transfer Acknowledge 1
These bits enable or disable clearing when
DMA transfer is performed for the internal
interrupt source selected by the DTF3 to DTF0
bits in DMACR of channel 1.
It the DTA1 bit is set to 1 when DTE1 = 1, the
internal interrupt source is cleared automatically
by DMA transfer. When DTE1 = 1 and DTA1 =
1, the internal interrupt source does not issue
an interrupt request to the CPU or DTC.
It the DTA1 bit is cleared to 0 when DTE1 = 1,
the internal interrupt source is not cleared when
a transfer is performed, and can issue an
interrupt request to the CPU or DTC in parallel.
In this case, the interrupt source should be
cleared by the CPU or DTC transfer.
When DTE1 = 0, the internal interrupt source
issues an interrupt request to the CPU or DTC
regardless of the DTA1 bit setting.
The state of the DTME1 bit does not affect the
above operations.
Reserved
These bits can be read from or written to.
Rev. 1.0, 09/01, page 259 of 904