Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 264

16 bit single-chip microcomputer
Table of Contents

Advertisement

ø
Address bus
Precharge-sel
CKE
DQMU, DQML
,
Data bus
Figure 6.73 Example of Idle Cycle Operation in RAS Down Mode
Rev. 1.0, 09/01, page 220 of 904
Continuous synchronous
DRAM space read
T
T
T
T
p
r
c1
cl
Row
Column
Column address 1
address
address
Row
address
PALL ACTV READ
(Read in Different Area) (IDLC = 0, CAS Latency 2)
External space read
T
T
T
T
c2
1
2
External address
External address
High
High
NOP
Continuous synchronous
DRAM space read
T
T
T
3
i
c1
Cl
Column address 2
READ
NOP
Idle cycle
T
c2

Hide quick links:

Advertisement

Table of Contents
loading

Table of Contents