Slave Receive Operation - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

SCL
9
(master output)
SDA
(master output)
SCL
A
(slave output)
SDA
(slave output)
TDRE
TEND
TRS
ICDRT
ICDRS
ICDRR
User
processing
Figure 16.10 Slave Transmit Mode Operation Timing 2
16.4.5

Slave Receive Operation

In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. For slave receive mode operation timing, refer to
figures 21.11 and 21.12. The reception procedure and operations in slave receive mode are
described below.
1. Set the ICE bit in ICCRA to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0
bits in ICCRA to 1. (Initial setting) Set the MST and TRS bits in ICCRA to select slave receive
mode, and wait until the slave address matches.
2. When the slave address matches in the first frame following detection of the start condition,
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th
clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read) and RDRF
is cleared. (Since the read data show the slave address and R/:, it is not used.)
3. Clear RDRF after reading ICDRR every time RDRF is set. If 8th receive clock pulse falls
while RDRF is 1, SCL is fixed low until RDRF is cleared. The change of the acknowledge
1 2 3 4
Bit 7 Bit 6 Bit 5 Bit 4
Data n
[3] Clear TEND
Slave transmit mode
5 6 7 8
Bit 3 Bit 2 Bit 1 Bit 0
[4] Read ICDRR (dummy read)
after clearing TRS
Rev. 1.0, 09/01, page 727 of 904
Slave receive
mode
9
[5] Clear TDRE