Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 300

• DMABCRL
Bit Bit Name
7 DTE1B
6 DTE1A
5 DTE0B
4 DTE0A
Rev. 1.0, 09/01, page 256 of 904
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
Description
Data Transfer Enable 1B
Data Transfer Enable 1A
Data Transfer Enable 0B
Data Transfer Enable 0A
If the DTIE bit is set to 1 when DTE = 0, the
DMAC regards this as indicating the end of a
transfer, and issues a transfer end interrupt
request to the CPU or DTC.
When DTE = 0, data transfer is enabled and the
DMAC ignores the activation source selected by
the DTF3 to DTF0 bits in DMACR.
When DTE = 1, data transfer is enabled and the
DMAC waits for a request by the activation
source selected by the DTF3 to DTF0 bits in
DMACR. When a request is issued by the
activation source, DMA transfer is executed.
[Clearing conditions]
•
When initialization is performed
•
When the specified number of transfers
have been completed in a transfer mode
other than repeat mode
•
When 0 is written to the DTE bit to forcibly
suspend the transfer, or for a similar reason
[Setting condition]
When 1 is written to the DTE bit after reading
DTE = 0