Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 170

Bit Bit Name
2 MXC2
1 MXC1
0 MXC0
Rev. 1.0, 09/01, page 126 of 904
Initial Value R/W
0 R/W
0 R/W
0 R/W
Description
Address Multiplex Select
These bits select the size of the shift toward the
lower half of the row address in row
address/column address multiplexing. In burst
operation on the DRAM/synchronous DRAM
interface, these bits also select the row address
bits to be used for comparison.
When the MXC2 bit is set to 1 while continuous
synchronous DRAM space is set, the address
precharge setting command (Precharge-sel) is
output to the upper column address. For details,
refer to sections 6.6.2 and 6.7.2, Address
Multiplex.
DRAM interface
000: 8-bit shift
•
When 8-bit access space is designated:
Row address bits A23 to A8 used for
comparison
•
When 16-bit access space is designated:
Row address bits A23 to A9 used for
comparison
001: 9-bit shift
•
When 8-bit access space is designated:
Row address bits A23 to A9 used for
comparison
•
When 16-bit access space is designated:
Row address bits A23 to A10 used for
comparison
010: 10-bit shift
•
When 8-bit access space is designated:
Row address bits A23 to A10 used for
comparison
•
When 16-bit access space is designated:
Row address bits A23 to A11 used for
comparison