Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 865

Register Name
I/O address register 1B
Transfer count register 1B
DMA write enable register
DMA terminal control register
DMA control register 0A
DMA control register 0B
DMA control register 1A
DMA control register 1B
DMA band control register H
DMA band control register L
DTC enable register A
DTC enable register B
DTC enable register C
DTC enable register D
DTC enable register E
DTC enable register F
DTC enable register G
DTC enable register H
DTC vector register
Interrupt control register
IRQ enable register
IRQ status register
Standby control register
System clock control register
System control register
Mode control register
Module stop control register H
Module stop control register L
Abbrevia-
tion Bit No.
IOAR_1B 16
ETCR_1B 16
DMAWER 8
DMATCR 8
DMACR_0A 8
DMACR_0B 8
DMACR_1A 8
DMACR_1B 8
DMABCRH 8
DMABCRL 8
DTCERA 8
DTCERB 8
DTCERC 8
DTCERD 8
DTCERE 8
DTCERF 8
DTCERG 8
DTCERH 8
DTVECR 8
INTCR 8
IER 16
ISR 16
SBYCR 8
SCKCR 8
SYSCR 8
MDCR 8
MSTPCRH 8
MSTPCRL 8
Address Module
H'FEFC DMAC
H'FEFE DMAC
H'FF20 DMAC
H'FF21 DMAC
H'FF22 DMAC
H'FF23 DMAC
H'FF24 DMAC
H'FF25 DMAC
H'FF26 DMAC
H'FF27 DMAC
H'FF28 DTC
H'FF29 DTC
H'FF2A DTC
H'FF2B DTC
H'FF2C DTC
H'FF2D DTC
H'FF2E DTC
H'FF2F DTC
H'FF30 DTC
H'FF31 INT
H'FF32 INT
H'FF34 INT
H'FF3A SYSTEM
H'FF3B SYSTEM
H'FF3D SYSTEM
H'FF3E SYSTEM
H'FF40 SYSTEM
H'FF41 SYSTEM
Rev. 1.0, 09/01, page 821 of 904
Data Access
Width States
16 2
16 2
8 2
8 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
16 2
8 2
8 2
8 2
8 2
8 2
8 2