Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 678

Normal Serial Communication Interface Mode (When SMIF in SCMR is 0)
Bit Bit Name
7 TIE
6 RIE
5 TE
4 RE
Rev. 1.0, 09/01, page 634 of 904
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
Description
Transmit Interrupt Enable
When this bit is set to 1, TXI interrupt request is
enabled.
TXI interrupt request cancellation can be
performed by reading 1 from the TDRE flag, then
clearing it to 0, or clearing the TIE bit to 0.
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt
requests are enabled.
RXI and ERI interrupt request cancellation can be
performed by reading 1 from the RDRF flag, or the
FER, PER, or ORER flag, then clearing the flag to
0, or by clearing the RIE bit to 0.
Transmit Enable
When this bit s set to 1, transmission is enabled.
In this state, serial transmission is started when
transmit data is written to TDR and the TDRE flag
in SSR is cleared to 0. SMR setting must be
performed to decide the transfer format before
setting the TE bit to 1.
The TDRE flag in SSR is fixed at 1 if transmission
is disabled by clearing this bit to 0.
Receive Enable
When this bit is set to 1, reception is enabled.
Ser i al r ecept i on i s st ar t ed i n t hi s st at e w hen a st ar t
bi t i s det ect ed i n asynchr onous m ode or ser i al
cl ock i nput i s det ect ed i n cl ocked synchr onous
m ode. SM R set t i ng m ust be per f or m ed t o deci de
t he t r ansf er f or m at bef or e set t i ng t he R E bi t t o 1.
C l ear i ng t he R E bi t t o 0 does not af f ect t he R D R F,
FER , PER , and O R ER f l ags, w hi ch r et ai n t hei r
st at es.