Location Of Register Information And Dtc Vector Table - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

Source flag cleared
Clear
controller
Clear
DTCER
Clear request
Select
On-chip
DTC
supporting
module
IRQ interrupt
Interrupt
request
CPU
Interrupt controller
DTVECR
Interrupt mask
Figure 9.2 Block Diagram of DTC Activation Source Control
9.4

Location of Register Information and DTC Vector Table

Locate the register information in the on-chip RAM (addresses: H'FFBC00 to H'FFBFFF).
Register information should be located at the address that is multiple of four within the range.
Locating the register information in address space is shown in figure 9.3. Locate the MRA, SAR,
MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register
information. In the case of chain transfer, register information should be located in consecutive
areas as shown in figure 9.3 and the register information start address should be located at the
corresponding vector address to the activation source. The DTC reads the start address of the
register information from the vector address set for each activation source, and then reads the
register information from that start address.
When the DTC is activated by software, the vector address is obtained from: H'0400 +
(DTVECR[6:0] × 2). For example, if DTVECR is H'10, the vector address is H'0420.
The configuration of the vector address is the same in both normal* and advanced modes, a 2-byte
unit being used in both cases. These two bytes specify the lower bits of the register information
start address.
Rev. 1.0, 09/01, page 385 of 904