Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 370

Bit Bit Name
5 TCEIE
4 SDIR
3 DTSIZE
2 BGUP
1 —
0 —
Note: * Only 0 can be written, to clear the flag.
Rev. 1.0, 09/01, page 326 of 904
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Description
Transfer Counter End Interrupt Enable
Enables or disables transfer end interrupt
requests by the transfer counter. When
transfer ends according to the transfer
counter while this bit is set to 1, the IRF bit
is set to 1, indicating that an interrupt
request has occurred.
0: Transfer end interrupt requests by
transfer counter are disabled
1: Transfer end interrupt requests by
transfer counter are enabled
Single Address Direction
Specifies the data transfer direction in
single address mode. In dual address
mode, the specification by this bit is
ignored.
0: Transfer direction: EDSAR → external
device with '$&.
1: Transfer direction: External device with
'$&.→ EDDAR
Data Transmit Size
Specifies the size of data to be transferred.
0: Byte-size
1: Word-size
Bus Give-Up
When this bit is set to 1, the bus can be
transferred to an internal bus master in
burst mode or block transfer mode. This
setting is ignored in normal mode and cycle
steal mode.
0: Bus is not released
1: Bus is transferred if requested by an
internal bus master
Reserved
These bits are always read as 0. The initial
values should not be modified.